Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...
Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ... Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...
5.1.30 MD—Message Data (D1:F0) .............................................................. 133 5.1.31 PEG_CAPL—PCI Express* Capability List (D1:F0) ........................... 134 5.1.32 PEG_CAP—PCI Express* Capabilities (D1:F0) ................................. 134 5.1.33 DCAP—Device Capabilities (D1:F0) .................................................. 135 5.1.34 DCTL—Device Control (D1:F0) .......................................................... 136 5.1.35 DSTS—Device Status (D1:F0) ........................................................... 137 5.1.36 LCAP—Link Capabilities (D1:F0) ....................................................... 138 5.1.37 LCTL—Link Control (D1:F0) ............................................................... 139 5.1.38 LSTS—Link Status (D1:F0) ................................................................ 140 5.1.39 SLOTCAP—Slot Capabilities (D1:F0) ................................................ 141 5.1.40 SLOTCTL—Slot Control (D1:F0) ........................................................ 142 5.1.41 SLOTSTS—Slot Status (D1:F0) ......................................................... 143 5.1.42 RCTL—Root Control (D1:F0) ............................................................. 144 5.1.43 RSTS—Root Status (D1:F0) ............................................................... 145 5.1.44 PEG_LC—PCI Express* Legacy Control (D1:F0) .............................. 146 5.1.45 VCECH—Virtual Channel Enhanced Capability Header (D1:F0) ...... 147 5.1.46 PVCCAP1—Port VC Capability Register 1 (D1:F0) ........................... 147 5.1.47 PVCCAP2—Port VC Capability Register 2 (D1:F0) ........................... 148 5.1.48 PVCCTL—Port VC Control (D1:F0) ................................................... 148 5.1.49 VC0RCAP—VC0 Resource Capability (D1:F0) ................................. 149 5.1.50 VC0RCTL—VC0 Resource Control (D1:F0) ...................................... 149 5.1.51 VC0RSTS—VC0 Resource Status (D1:F0) ........................................ 150 5.1.52 VC1RCAP—VC1 Resource Capability (D1:F0) ................................. 150 5.1.53 VC1RCTL—VC1 Resource Control (D1:F0) ...................................... 151 5.1.54 VC1RSTS—VC1 Resource Status (D1:F0) ........................................ 152 5.1.55 RCLDECH—Root Complex Link Declaration Enhanced Capability Header (D1:F0) ................................................................................... 152 5.1.56 ESD—Element Self Description (D1:F0) ............................................ 153 5.1.57 LE1D—Link Entry 1 Description (D1:F0) ............................................ 154 5.1.58 LE1A—Link Entry 1 Address (D1:F0) ................................................. 154 5.1.59 UESTS—Uncorrectable Error Status (D1:F0) .................................... 155 5.1.60 UEMSK—Uncorrectable Error Mask (D1:F0) ..................................... 156 5.1.61 CESTS—Correctable Error Status (D1:F0) ........................................ 157 5.1.62 CEMSK—Correctable Error Mask (D1:F0) ......................................... 158 5.1.63 PEG_SSTS—PCI Express* Sequence Status (D1:F0) ...................... 159 6 Direct Media Interface (DMI) RCRB................................................................................ 161 6.1 DMI RCRB Configuration Register Details ......................................................... 162 6.1.1 DMIVCECH—DMI Virtual Channel Enhanced Capability Header ..... 162 6.1.2 DMIPVCCAP1—DMI Port VC Capability Register 1 .......................... 162 6.1.3 DMIPVCCAP2—DMI Port VC Capability Register 2 .......................... 163 6.1.4 DMIPVCCTL—DMI Port VC Control .................................................. 163 6.1.5 DMIVC0RCAP—DMI VC0 Resource Capability ................................ 164 6.1.6 DMIVC0RCTL—DMI VC0 Resource Control ..................................... 165 6.1.7 DMIVC0RSTS—DMI VC0 Resource Status ....................................... 166 6.1.8 DMIVC1RCAP—DMI VC1 Resource Capability ................................ 166 6.1.9 DMIVC1RCTL—DMI VC1 Resource Control ..................................... 167 6.1.10 DMIVC1RSTS—DMI VC1 Resource Status ....................................... 167 6.1.11 DMILCAP—DMI Link Capabilities ...................................................... 168 6.1.12 DMILCTL—DMI Link Control .............................................................. 168 6.1.13 DMILSTS—DMI Link Status ............................................................... 169 6.1.14 DMIUESTS—DMI Uncorrectable Error Status ................................... 170 6.1.15 DMIUEMSK—DMI Uncorrectable Error Mask .................................... 171 6 Intel ® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
6.1.16 DMICESTS—DMI Correctable Error Status ....................................... 172 7 Integrated Graphics Device (D2:F0) (Intel ® 82945G/82945GC/ 82945GZ GMCH Only)173 7.1 Configuration Register Details (D2:F0) .............................................................. 175 7.1.1 VID2—Vendor Identification (D2:F0) .................................................. 175 7.1.2 DID2—Device Identification (D2:F0) .................................................. 175 7.1.3 PCICMD2—PCI Command (D2:F0) ................................................... 176 7.1.4 PCISTS2—PCI Status (D2:F0) ........................................................... 177 7.1.5 RID2—Revision Identification (D2:F0) ................................................ 178 7.1.6 CC—Class Code (D2:F0) ................................................................... 178 7.1.7 CLS—Cache Line Size (D2:F0) .......................................................... 179 7.1.8 MLT2—Master Latency Timer (D2:F0) ............................................... 179 7.1.9 HDR2—Header Type (D2:F0) ............................................................ 179 7.1.10 MMADR—Memory Mapped Range Address (D2:F0) ........................ 180 7.1.11 IOBAR—I/O Base Address (D2:F0) ................................................... 181 7.1.12 GMADR—Graphics Memory Range Address (D2:F0) ....................... 182 7.1.13 GTTADR—Graphics Translation Table Range Address (D2:F0) ....... 182 7.1.14 SVID2—Subsystem Vendor Identification (D2:F0) ............................. 183 7.1.15 SID2—Subsystem Identification (D2:F0) ............................................ 183 7.1.16 ROMADR—Video BIOS ROM Base Address (D2:F0) ....................... 183 7.1.17 CAPPOINT—Capabilities Pointer (D2:F0) ......................................... 184 7.1.18 INTRLINE—Interrupt Line (D2:F0) ..................................................... 184 7.1.19 INTRPIN—Interrupt Pin (D2:F0) ......................................................... 184 7.1.20 MINGNT—Minimum Grant (D2:F0) .................................................... 185 7.1.21 MAXLAT—Maximum Latency (D2:F0) ............................................... 185 7.1.22 MCAPPTR—Mirror of Device 0 Capability Pointer (D2:F0) (Mirrored_D0_34) ............................................................................... 185 7.1.23 MCAPID—Mirror of Device 0 Capability Identification (D2:F0) (Mirrored_D0_E0) ............................................................................... 185 7.1.24 MGGC—Mirror of Device 0 GMCH Graphics Control (D2:F0) (Mirrored_D0_52) ............................................................................... 186 7.1.25 MDEVEN—Mirror of Device 0 Device Enable (D2:F0) (Mirrored_D0_54) ............................................................................... 186 7.1.26 BSM—Base of “Stolen” Memory (D2:F0) ........................................... 186 7.1.27 PMCAPID—Power Management Capabilities ID (D2:F0) .................. 187 7.1.28 PMCAP—Power Management Capabilities (D2:F0) .......................... 187 7.1.29 PMCS—Power Management Control/Status (D2:F0) ........................ 188 7.1.30 SWSMI—Software SMI (D2:F0) ......................................................... 188 7.1.31 ASLE—System Display Event Register (D2:F0) ................................ 189 7.1.32 ASLS—ASL Storage (D2:F0) ............................................................. 189 8 Integrated Graphics Device (D2:F1) Registers (Intel ® 82945G/82945GC/82945GZ GMCH Only) .................................................................................................................... 191 8.1.1 VID2—Vendor Identification (D2:F1) .................................................. 192 8.1.2 DID2—Device Identification (D2:F1) .................................................. 192 8.1.3 PCICMD2—PCI Command (D2:F1) ................................................... 193 8.1.4 PCISTS2—PCI Status (D2:F1) ........................................................... 194 8.1.5 RID2—Revision Identification (D2:F1) ................................................ 195 8.1.6 CC—Class Code Register (D2:F1) ..................................................... 195 8.1.7 CLS—Cache Line Size (D2:F1) .......................................................... 196 8.1.8 MLT2—Master Latency Timer (D2:F1) ............................................... 196 8.1.9 HDR2—Header Type Register (D2:F1) .............................................. 196 8.1.10 MMADR—Memory Mapped Range Address (D2:F1) ........................ 197 Intel ® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet 7
- Page 1 and 2: Intel ® 945G/945GZ/945GC/ 945P/945
- Page 3 and 4: Contents 1 Introduction ...........
- Page 5: 4.2.11 C0DRC1—Channel A DRAM Cont
- Page 9 and 10: 9.4.5 SMM Space Decode and Transact
- Page 11 and 12: 11.3 DC Characteristics ...........
- Page 13 and 14: Revision History Rev Description Da
- Page 15 and 16: Intel ® 82945G/82945GZ/82945GC/829
- Page 17 and 18: 1 Introduction Introduction The Int
- Page 19 and 20: Figure 1-2. Intel ® 945GZ/82945GC
- Page 21 and 22: 1.1 Terminology Term Description Ac
- Page 23 and 24: Term Description TOLM Top Of Low Me
- Page 25 and 26: Introduction � Supports four bank
- Page 27 and 28: Introduction 1.4 Graphics (Intel ®
- Page 29 and 30: 1.5 Analog and SDVO Displays (Intel
- Page 31 and 32: 2 Signal Description Signal Descrip
- Page 33 and 34: 2.1 Host Interface Signals Signal D
- Page 35 and 36: Signal Name Type Description HREQ[4
- Page 37 and 38: 2.3 DDR2 DRAM Channel B Interface S
- Page 39 and 40: Signal Description 2.6 Analog Displ
- Page 41 and 42: 2.8 Direct Media Interface (DMI) Si
- Page 43 and 44: 2.10 Power and Ground Name Voltage
- Page 45 and 46: Interface Signal Name I/O System Me
- Page 47 and 48: Interface Signal Name I/O State Dur
- Page 49 and 50: 3 Register Description Register Des
- Page 51 and 52: Register Description Note: A physic
- Page 53 and 54: 3.3 Configuration Mechanisms Regist
- Page 55 and 56: 3.4 Routing Configuration Accesses
6.1.16 DMICESTS—DMI Correctable Error Status ....................................... 172<br />
7 Integrated Graphics Device (D2:F0) (Intel ® 82<strong>945G</strong>/82<strong>945G</strong>C/ 82<strong>945G</strong>Z GMCH Only)173<br />
7.1 Configuration Register Details (D2:F0) .............................................................. 175<br />
7.1.1 VID2—Vendor Identification (D2:F0) .................................................. 175<br />
7.1.2 DID2—Device Identification (D2:F0) .................................................. 175<br />
7.1.3 PCICMD2—PCI Command (D2:F0) ................................................... 176<br />
7.1.4 PCISTS2—PCI Status (D2:F0) ........................................................... 177<br />
7.1.5 RID2—Revision Identification (D2:F0) ................................................ 178<br />
7.1.6 CC—Class Code (D2:F0) ................................................................... 178<br />
7.1.7 CLS—Cache Line Size (D2:F0) .......................................................... 179<br />
7.1.8 MLT2—Master Latency Timer (D2:F0) ............................................... 179<br />
7.1.9 HDR2—Header Type (D2:F0) ............................................................ 179<br />
7.1.10 MMADR—Memory Mapped Range Address (D2:F0) ........................ 180<br />
7.1.11 IOBAR—I/O Base Address (D2:F0) ................................................... 181<br />
7.1.12 GMADR—Graphics Memory Range Address (D2:F0) ....................... 182<br />
7.1.13 GTTADR—Graphics Translation Table Range Address (D2:F0) ....... 182<br />
7.1.14 SVID2—Subsystem Vendor Identification (D2:F0) ............................. 183<br />
7.1.15 SID2—Subsystem Identification (D2:F0) ............................................ 183<br />
7.1.16 ROMADR—Video BIOS ROM Base Address (D2:F0) ....................... 183<br />
7.1.17 CAPPOINT—Capabilities Pointer (D2:F0) ......................................... 184<br />
7.1.18 INTRLINE—Interrupt Line (D2:F0) ..................................................... 184<br />
7.1.19 INTRPIN—Interrupt Pin (D2:F0) ......................................................... 184<br />
7.1.20 MINGNT—Minimum Grant (D2:F0) .................................................... 185<br />
7.1.21 MAXLAT—Maximum Latency (D2:F0) ............................................... 185<br />
7.1.22 MCAPPTR—Mirror of Device 0 Capability Pointer (D2:F0)<br />
(Mirrored_D0_34) ............................................................................... 185<br />
7.1.23 MCAPID—Mirror of Device 0 Capability Identification (D2:F0)<br />
(Mirrored_D0_E0) ............................................................................... 185<br />
7.1.24 MGGC—Mirror of Device 0 GMCH Graphics Control (D2:F0)<br />
(Mirrored_D0_52) ............................................................................... 186<br />
7.1.25 MDEVEN—Mirror of Device 0 Device Enable (D2:F0)<br />
(Mirrored_D0_54) ............................................................................... 186<br />
7.1.26 BSM—Base of “Stolen” Memory (D2:F0) ........................................... 186<br />
7.1.27 PMCAPID—Power Management Capabilities ID (D2:F0) .................. 187<br />
7.1.28 PMCAP—Power Management Capabilities (D2:F0) .......................... 187<br />
7.1.29 PMCS—Power Management Control/Status (D2:F0) ........................ 188<br />
7.1.30 SWSMI—Software SMI (D2:F0) ......................................................... 188<br />
7.1.31 ASLE—System Display Event Register (D2:F0) ................................ 189<br />
7.1.32 ASLS—ASL Storage (D2:F0) ............................................................. 189<br />
8 Integrated Graphics Device (D2:F1) Registers (Intel ® 82<strong>945G</strong>/82<strong>945G</strong>C/82<strong>945G</strong>Z<br />
GMCH Only) .................................................................................................................... 191<br />
8.1.1 VID2—Vendor Identification (D2:F1) .................................................. 192<br />
8.1.2 DID2—Device Identification (D2:F1) .................................................. 192<br />
8.1.3 PCICMD2—PCI Command (D2:F1) ................................................... 193<br />
8.1.4 PCISTS2—PCI Status (D2:F1) ........................................................... 194<br />
8.1.5 RID2—Revision Identification (D2:F1) ................................................ 195<br />
8.1.6 CC—Class Code Register (D2:F1) ..................................................... 195<br />
8.1.7 CLS—Cache Line Size (D2:F1) .......................................................... 196<br />
8.1.8 MLT2—Master Latency Timer (D2:F1) ............................................... 196<br />
8.1.9 HDR2—Header Type Register (D2:F1) .............................................. 196<br />
8.1.10 MMADR—Memory Mapped Range Address (D2:F1) ........................ 197<br />
Intel ® 82<strong>945G</strong>/82<strong>945G</strong>/82<strong>945G</strong>C GMCH and 82<strong>945P</strong>/82<strong>945P</strong>L MCH Datasheet 7
Change language