Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

4.1.12 EPBAR—Egress Port Base Address (D0:F0)
PCI Device: 0
Address Offset: 40h
Default Value: 00000000h
Access: RO
Size: 32 bits
Host Bridge/DRAM Controller Registers (D0:F0)
This is the base address for the Egress Port MMIO configuration space. There is no physical
memory within this 4-KB window that can be addressed. The 4 KB reserved by this register does
not alias to any PCI 2.3 compliant memory-mapped space.
On reset, the Egress Port MMIO Base Address field in this register is disabled and must be
enabled by writing a 1 to the EPBAREN bit.
Bit Access &
Default
31:12 R/W
00000h
11:1 Reserved
0 R/W
0b
Description
Egress Port MMIO Base Address: This field corresponds to bits 31:12 of the
base address Egress Port MMIO configuration space.
BIOS will program this register resulting in a base address for a 4-KB block of
contiguous memory address space. This register ensures that a naturally aligned
4-KB space is allocated within total addressable memory space of 4 GB.
System software uses this base address to program the (G)MCH MMIO register
set.
EPBAR Enable (EPBAREN):
0 = EPBAR is disabled and does not claim any memory.
1 = EPBAR memory-mapped accesses are claimed and decoded appropriately.
Intel ® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet 69