Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

Host Bridge/DRAM Controller Registers (D0:F0)
Bit Access &
Default
4 RO
1b
3:0 Reserved
Description
Capability List (CLIST): Hardwired to 1 to indicate to the configuration software
that this device/function implements a list of new capabilities. A list of new
capabilities is accessed via the CAPPTR register (address offset 34h). The
CAPPTR register contains an offset pointing to the start address within
configuration space of this device where the Capability standard register resides.
4.1.5 RID—Revision Identification (D0:F0)
PCI Device: 0
Address Offset: 08h
Default Value: See bit description
Access: RO
Size: 8 bits
This register contains the revision number of the (G)MCH Device 0.
Bit Access &
Default
Description
7:0 RO Revision Identification Number (RID): This is an 8-bit value that indicates the
revision identification number for the (G)MCH Device 0. Refer to the Intel ®
945G/945GC/945GZ/945P/945PL Express Chipset Specification Update for the
value of the Revision ID register.
4.1.6 CC—Class Code (D0:F0)
PCI Device: 0
Address Offset: 09h
Default Value: 060000h
Access: RO
Size: 24 bits
This register identifies the basic function of the device, a more specific sub-class, and a registerspecific
programming interface.
Bit Access &
Default
23:16 RO
06h
15:8 RO
00h
7:0 RO
00h
Description
Base Class Code (BCC): This is an 8-bit value that indicates the base class code
for the (G)MCH.
06h = Bridge device.
Sub-Class Code (SUBCC): This is an 8-bit value that indicates the category of
bridge for the (G)MCH.
00h = Host Bridge.
Programming Interface (PI): This is an 8-bit value that indicates the programming
interface of this device. This value does not specify a particular register set layout
and provides no practical use for this device.
66 Intel ® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet