Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

Host Bridge/DRAM Controller Registers (D0:F0)
4 Host Bridge/DRAM Controller
Registers (D0:F0)
The DRAM Controller registers are in Device 0 (D0), Function 0 (F0). Table 4-1 provides an
address map of the D0:F0 registers listed by address offset in ascending order. Section 4.1
provides a detailed bit description of the registers.
Warning: Address locations that are not listed are considered Intel Reserved registers locations. Reads to
reserved register locations may return non-zero values. Writes to reserved locations may cause
system failures.
All registers that are defined in the PCI 2.3 specification, but are not necessary or implemented in
this component are simply not included in this document. The reserved/unimplemented space in
the PCI configuration header space is not documented as such in this summary.
Table 4-1. Host Bridge/DRAM Controller Register Address Map (D0:F0)
Address
Offset
Symbol Register Name
Default
Value
Access
00–01h VID Vendor Identification 8086h RO
02–03h DID Device Identification 2770h RO
04–05h PCICMD PCI Command 0006h RO, R/W
06–07h PCISTS PCI Status 0090h RO, R/WC
08h RID Revision Identification see register
description
09–0Bh CC Class Code 00h RO
0Ch — Reserved — —
0Dh MLT Master Latency Timer 00h RO
0Eh HDR Header Type 00h RO
0F–2Bh — Reserved — —
2C–2Dh SVID Subsystem Vendor Identification 0000h R/WO
2E–2Fh SID Subsystem Identification 0000h R/WO
30–33h — Reserved — —
34h CAPPTR Capabilities Pointer E0h RO
35–3Fh — Reserved — —
40–43h EPBAR Egress Port Base Address 00000000h RO
44–47h MCHBAR GMCH Memory Mapped Register Range
Base Address
Intel ® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet 61
RO
00000000h R/W