Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...
Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ... Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...
Register Description 60 Intel ® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
Host Bridge/DRAM Controller Registers (D0:F0) 4 Host Bridge/DRAM Controller Registers (D0:F0) The DRAM Controller registers are in Device 0 (D0), Function 0 (F0). Table 4-1 provides an address map of the D0:F0 registers listed by address offset in ascending order. Section 4.1 provides a detailed bit description of the registers. Warning: Address locations that are not listed are considered Intel Reserved registers locations. Reads to reserved register locations may return non-zero values. Writes to reserved locations may cause system failures. All registers that are defined in the PCI 2.3 specification, but are not necessary or implemented in this component are simply not included in this document. The reserved/unimplemented space in the PCI configuration header space is not documented as such in this summary. Table 4-1. Host Bridge/DRAM Controller Register Address Map (D0:F0) Address Offset Symbol Register Name Default Value Access 00–01h VID Vendor Identification 8086h RO 02–03h DID Device Identification 2770h RO 04–05h PCICMD PCI Command 0006h RO, R/W 06–07h PCISTS PCI Status 0090h RO, R/WC 08h RID Revision Identification see register description 09–0Bh CC Class Code 00h RO 0Ch — Reserved — — 0Dh MLT Master Latency Timer 00h RO 0Eh HDR Header Type 00h RO 0F–2Bh — Reserved — — 2C–2Dh SVID Subsystem Vendor Identification 0000h R/WO 2E–2Fh SID Subsystem Identification 0000h R/WO 30–33h — Reserved — — 34h CAPPTR Capabilities Pointer E0h RO 35–3Fh — Reserved — — 40–43h EPBAR Egress Port Base Address 00000000h RO 44–47h MCHBAR GMCH Memory Mapped Register Range Base Address Intel ® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet 61 RO 00000000h R/W
- Page 9 and 10: 9.4.5 SMM Space Decode and Transact
- Page 11 and 12: 11.3 DC Characteristics ...........
- Page 13 and 14: Revision History Rev Description Da
- Page 15 and 16: Intel ® 82945G/82945GZ/82945GC/829
- Page 17 and 18: 1 Introduction Introduction The Int
- Page 19 and 20: Figure 1-2. Intel ® 945GZ/82945GC
- Page 21 and 22: 1.1 Terminology Term Description Ac
- Page 23 and 24: Term Description TOLM Top Of Low Me
- Page 25 and 26: Introduction � Supports four bank
- Page 27 and 28: Introduction 1.4 Graphics (Intel ®
- Page 29 and 30: 1.5 Analog and SDVO Displays (Intel
- Page 31 and 32: 2 Signal Description Signal Descrip
- Page 33 and 34: 2.1 Host Interface Signals Signal D
- Page 35 and 36: Signal Name Type Description HREQ[4
- Page 37 and 38: 2.3 DDR2 DRAM Channel B Interface S
- Page 39 and 40: Signal Description 2.6 Analog Displ
- Page 41 and 42: 2.8 Direct Media Interface (DMI) Si
- Page 43 and 44: 2.10 Power and Ground Name Voltage
- Page 45 and 46: Interface Signal Name I/O System Me
- Page 47 and 48: Interface Signal Name I/O State Dur
- Page 49 and 50: 3 Register Description Register Des
- Page 51 and 52: Register Description Note: A physic
- Page 53 and 54: 3.3 Configuration Mechanisms Regist
- Page 55 and 56: 3.4 Routing Configuration Accesses
- Page 57 and 58: 3.4.2.2 DMI Configuration Accesses
- Page 59: Bit Access & Default 10:8 R/W 000b
- Page 63 and 64: 4.1 Device 0 Configuration Register
- Page 65 and 66: 4.1.4 PCISTS—PCI Status (D0:F0) P
- Page 67 and 68: 4.1.7 MLT—Master Latency Timer (D
- Page 69 and 70: 4.1.12 EPBAR—Egress Port Base Add
- Page 71 and 72: Host Bridge/DRAM Controller Registe
- Page 73 and 74: Host Bridge/DRAM Controller Registe
- Page 75 and 76: Host Bridge/DRAM Controller Registe
- Page 77 and 78: 4.1.19 PAM1—Programmable Attribut
- Page 79 and 80: 4.1.21 PAM3—Programmable Attribut
- Page 81 and 82: 4.1.23 PAM5—Programmable Attribut
- Page 83 and 84: 4.1.25 LAC—Legacy Access Control
- Page 85 and 86: Host Bridge/DRAM Controller Registe
- Page 87 and 88: 4.1.29 ERRSTS—Error Status (D0:F0
- Page 89 and 90: 4.1.31 SKPD—Scratchpad Data (D0:F
- Page 91 and 92: Host Bridge/DRAM Controller Registe
- Page 93 and 94: Host Bridge/DRAM Controller Registe
- Page 95 and 96: 4.2.7 C0DCLKDIS—Channel A DRAM Cl
- Page 97 and 98: 4.2.9 C0DRT1—Channel A DRAM Timin
- Page 99 and 100: Bit Access & Default 6:4 R/W 000b 3
- Page 101 and 102: Host Bridge/DRAM Controller Registe
- Page 103 and 104: 4.2.24 PMSTS—Power Management Sta
- Page 105 and 106: 4.3.1 EPESD—EP Element Self Descr
- Page 107 and 108: 4.3.3 EPLE1A—EP Link Entry 1 Addr
- Page 109 and 110: Host-PCI Express* Bridge Registers
Register Description<br />
60 Intel ® 82<strong>945G</strong>/82<strong>945G</strong>Z/82<strong>945G</strong>C GMCH and 82<strong>945P</strong>/82<strong>945P</strong>L MCH Datasheet
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