Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

Register Description
The PCI Express enhanced configuration mechanism uses a flat memory-mapped address space to
access device configuration registers. This address space is reported by the system firmware to the
operating system. The PCIEXBAR register defines the base address for the block of addresses
below 4 GB for the configuration space associated with busses, devices, and functions that are
potentially a part of the PCI Express root complex hierarchy. The PCIEXBAR register contains
controls to limit the size of this reserved memory-mapped space; 256 MB is the amount of
address space required to reserve space for every bus, device, and function is currently available.
Options for 128 MB and 64 MB are available to free up those addresses for other uses. In these
cases the number of busses and all of their associated devices and functions are limited to 128 or
64 busses respectively.
The PCI Express configuration transaction header includes an additional 4 bits
(ExtendedRegisterAddress[3:0]) between the function number and register address fields to
provide indexing into the 4 KB of configuration space allocated to each potential device. For PCI
compatible configuration requests, the Extended Register Address field must be all zeros.
Figure 3-3. Memory Map-to-PCI Express* Device Configuration Space
FFFFFFFh
1FFFFFh
FFFFFh
0h
Located By PCI
Express Base
Address
Bus 255
Bus 1
Bus 0
FFFFFh
FFFFh
7FFFh
Device 31
Device 1
Device 0
Function 7
MemMap_PCIExpress
54 Intel ® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
7FFFh
1FFFh
FFFh
Function 1
Function 0
FFFh
FFh
3Fh
PCI Express*
Extended
Configuration
Space
PCI
Compatible
Config Space
PCI
Compatible
Config Header
As with PCI devices, each PCI Express device is selected based on decoded address information
that is provided as a part of the address portion of configuration request packets. A PCI Express
device will decode all address information fields (bus, device, function, and extended address
numbers) to provide access to the correct register.
To access this space (steps 1, 2, and 3 are completed only once by BIOS):
1. use the PCI compatible configuration mechanism to enable the PCI Express enhanced
configuration mechanism by writing 1 to bit 0 of the PCIEXBAR register.
2. use the PCI compatible configuration mechanism to write an appropriate PCI Express
base address into the PCIEXBAR register .
3. calculate the host address of the register you wish to set using (PCI Express base +
(bus number * 1 MB) + (device number * 32 KB) + (function number * 4 KB) +
(1 B * offset within the function) = host address).
4. use a memory write or memory read cycle to the calculated host address to write or read
that register.