Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

3.3 Configuration Mechanisms
Register Description
The processor is the originator of configuration cycles; thus, the FSB is the only interface in the
platform where these mechanisms are used. The MCH translates transactions received through
both configuration mechanisms to the same format.
3.3.1 Standard PCI Configuration Mechanism
The following is the mechanism for translating processor I/O bus cycles to configuration cycles.
The PCI specification defines a slot based "configuration space" that allows each device to
contain up to 8 functions with each function containing up to 256 8-bit configuration registers.
The PCI specification defines two bus cycles to access the PCI configuration space: Configuration
Read and Configuration Write. Memory and I/O spaces are supported directly by the processor.
Configuration space is supported by a mapping mechanism implemented within the (G)MCH.
The configuration access mechanism uses the CONFIG_ADDRESS register (at I/O address
0CF8h though 0CFBh) and CONFIG_DATA register (at I/O address 0CFCh though 0CFFh). To
reference a configuration register, a DWord I/O write cycle is used to place a value into
CONFIG_ADDRESS that specifies the PCI bus, the device on that bus, the function within the
device, and a specific configuration register of the device function being accessed.
CONFIG_ADDRESS[31] must be 1 to enable a configuration cycle. CONFIG_DATA then
becomes a window into the four bytes of configuration space specified by the contents of
CONFIG_ADDRESS. Any read or write to CONFIG_DATA will result in the (G)MCH
translating the CONFIG_ADDRESS into the appropriate configuration cycle.
The (G)MCH is responsible for translating and routing the processor’s I/O accesses to the
CONFIG_ADDRESS and CONFIG_DATA registers to internal (G)MCH configuration registers,
DMI, or PCI Express.
3.3.2 PCI Express* Enhanced Configuration Mechanism (Intel ®
82945G/82945GC/82945P/82945PL (G)MCH Only)
PCI Express extends the configuration space to 4096 bytes per device/function as compared to
256 bytes allowed by the PCI Local Bus Specification, Revision 2.3. PCI Express configuration
space is divided into a PCI 2.3 compatible region that consists of the first 256B of a logical
device’s configuration space and a PCI Express extended region that consists of the remaining
configuration space.
The PCI compatible region can be accessed using either the Standard PCI configuration
mechanism or using the PCI Express enhanced configuration mechanism described in this section.
The extended configuration registers may only be accessed using the PCI Express enhanced
configuration mechanism. To maintain compatibility with PCI configuration addressing
mechanisms, system software must access the extended configuration space using
32-bit operations (32-bit aligned) only. These 32-bit operations include byte enables allowing
only appropriate bytes within the DWord to be accessed. Locked transactions to the PCI Express
memory-mapped configuration address space are not supported. All changes made using either
access mechanism are equivalent.
Intel ® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet 53