Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

Register Description
3.1 Register Terminology
The following table shows the register-related terminology that is used.
Item Description
RO Read Only bit(s). Writes to these bits have no effect.
RS/WC Read Set / Write Clear bit(s). These bits are set to 1 when read and then will continue to
remain set until written. A write of 1 clears (sets to ‘0’) the corresponding bit(s) and a write
of 0 has no effect.
R/W Read / Write bit(s). These bits can be read and written.
R/WC Read / Write Clear bit(s). These bits can be read. Internal events may set this bit. A write of
1 clears (sets to 0) the corresponding bit(s) and a write of 0 has no effect.
R/WC/S Read / Write Clear / Sticky bit(s). These bits can be read. Internal events may set this bit. A
write of 1 clears (sets to 0) the corresponding bit(s) and a write of 0 has no effect. Bits are
not cleared by "warm" reset, but will be reset with a cold/complete reset (for PCI Express*
related bits a cold reset is “Power Good Reset” as defined in the PCI Express*
Specification).
R/W/L Read / Write / Lockable bit(s). These bits can be read and written. Additionally, there is a
bit (which may or may not be a bit marked R/W/L) that, when set, prohibits this bit field
from being writeable (bit field becomes Read Only).
R/W/S Read / Write / Sticky bit(s). These bits can be read and written. Bits are not cleared by
"warm" reset, but will be reset with a cold/complete reset (for PCI Express related bits a
cold reset is “Power Good Reset” as defined in the PCI Express* Specification).
R/WSC Read / Write Self Clear bit(s). These bits can be read and written. When the bit is 1,
hardware may clear the bit to 0 based upon internal events, possibly sooner than any
subsequent read could retrieve a 1.
R/WSC/L Read / Write Self Clear / Lockable bit(s). These bits can be read and written. When the bit
is 1, hardware may clear the bit to 0 based upon internal events, possibly sooner than any
subsequent read could retrieve a 1. Additionally there is a bit (which may or may not be a
bit marked R/W/L) that, when set, prohibits this bit field from being writeable (bit field
becomes Read Only).
R/WO Write Once bit(s). Once written, bits with this attribute become Read Only. These bits can
only be cleared by a Reset.
W Write Only. Registers with this attribute have bits that may be written, but will always-return
zeros when read. They are used for write side effects. Any data written to these registers
cannot be retrieved.
3.2 Platform Configuration
In platforms that support DMI (such as, this (G)MCH) the configuration structure is significantly
different from hub architectures prior to the Intel ® 915x Express chipsets. The DMI physically
connects the (G)MCH and the ICH7; thus, from a configuration standpoint, the DMI is logically
PCI bus 0. As a result, all devices internal to the (G)MCH and the ICH7 appear to be on PCI
bus 0.
Note: The ICH7 internal LAN controller does not appear on bus 0; it appears on the external PCI bus
(bus number is configurable).
The system’s primary PCI expansion bus is physically attached to the ICH7 and, from a
configuration perspective, appears to be a hierarchical PCI bus behind a PCI-to-PCI bridge and,
therefore, has a programmable PCI bus number. The PCI Express graphics attach appears to
system software to be a real PCI bus behind a PCI-to-PCI bridge that is a device resident on PCI
bus 0.
50 Intel ® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet