Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...
Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ... Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...
3.4.2.2 DMI Configuration Accesses ............................................... 57 3.5 I/O Mapped Registers .......................................................................................... 57 3.5.1 CONFIG_ADDRESS—Configuration Address Register ...................... 58 3.5.2 CONFIG_DATA—Configuration Data Register .................................... 59 4 Host Bridge/DRAM Controller Registers (D0:F0) ............................................................. 61 4.1 Device 0 Configuration Register Details .............................................................. 63 4.1.1 VID—Vendor Identification (D0:F0) ...................................................... 63 4.1.2 DID—Device Identification (D0:F0) ...................................................... 63 4.1.3 PCICMD—PCI Command (D0:F0) ....................................................... 64 4.1.4 PCISTS—PCI Status (D0:F0) ............................................................... 65 4.1.5 RID—Revision Identification (D0:F0) .................................................... 66 4.1.6 CC—Class Code (D0:F0) ..................................................................... 66 4.1.7 MLT—Master Latency Timer (D0:F0) ................................................... 67 4.1.8 HDR—Header Type (D0:F0) ................................................................ 67 4.1.9 SVID—Subsystem Vendor Identification (D0:F0) ................................. 67 4.1.10 SID—Subsystem Identification (D0:F0) ................................................ 68 4.1.11 CAPPTR—Capabilities Pointer (D0:F0) ............................................... 68 4.1.12 EPBAR—Egress Port Base Address (D0:F0) ...................................... 69 4.1.13 MCHBAR—(G)MCH Memory Mapped Register Range Base Address (D0:F0) .................................................................................................. 70 4.1.14 PCIEXBAR—PCI Express* Register Range Base Address (D0:F0) (Intel ® 82945G/82945GC/82945P/82945PL (G)MCH Only) ................. 71 4.1.15 DMIBAR—Root Complex Register Range Base Address (D0:F0) ...... 73 4.1.16 GGC—GMCH Graphics Control Register (D0:F0) (Intel ® 82945G/82945GC/82945GZ GMCH Only) .......................................... 74 4.1.17 DEVEN—Device Enable (D0:F0) ......................................................... 75 4.1.18 PAM0—Programmable Attribute Map 0 (D0:F0) .................................. 76 4.1.19 PAM1—Programmable Attribute Map 1 (D0:F0) .................................. 77 4.1.20 PAM2—Programmable Attribute Map 2 (D0:F0) .................................. 78 4.1.21 PAM3—Programmable Attribute Map 3 (D0:F0) .................................. 79 4.1.22 PAM4—Programmable Attribute Map 4 (D0:F0) .................................. 80 4.1.23 PAM5—Programmable Attribute Map 5 (D0:F0) .................................. 81 4.1.24 PAM6—Programmable Attribute Map 6 (D0:F0) .................................. 82 4.1.25 LAC—Legacy Access Control (D0:F0) ................................................. 83 4.1.26 TOLUD—Top of Low Usable DRAM (D0:F0) ....................................... 84 4.1.27 SMRAM—System Management RAM Control (D0:F0) ........................ 85 4.1.28 ESMRAMC—Extended System Management RAM Control (D0:F0) .. 86 4.1.29 ERRSTS—Error Status (D0:F0) ........................................................... 87 4.1.30 ERRCMD—Error Command (D0:F0) ................................................... 88 4.1.31 SKPD—Scratchpad Data (D0:F0) ........................................................ 89 4.1.32 CAPID0—Capability Identifier (D0:F0) ................................................. 89 4.2 MCHBAR Register ............................................................................................... 90 4.2.1 C0DRB0—Channel A DRAM Rank Boundary Address 0 .................... 91 4.2.2 C0DRB1—Channel A DRAM Rank Boundary Address 1 .................... 93 4.2.3 C0DRB2—Channel A DRAM Rank Boundary Address 2 .................... 93 4.2.4 C0DRB3—Channel A DRAM Rank Boundary Address 3 .................... 93 4.2.5 C0DRA0—Channel A DRAM Rank 0,1 Attribute ................................. 94 4.2.6 C0DRA2—Channel A DRAM Rank 2,3 Attribute ................................. 94 4.2.7 C0DCLKDIS—Channel A DRAM Clock Disable .................................. 95 4.2.8 C0BNKARC—Channel A DRAM Bank Architecture ............................ 96 4.2.9 C0DRT1—Channel A DRAM Timing Register ..................................... 97 4.2.10 C0DRC0—Channel A DRAM Controller Mode 0 ................................. 98 4 Intel ® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
4.2.11 C0DRC1—Channel A DRAM Controller Mode 1 ............................... 100 4.2.12 C1DRB0—Channel B DRAM Rank Boundary Address 0 .................. 100 4.2.13 C1DRB1—Channel B DRAM Rank Boundary Address 1 .................. 100 4.2.14 C1DRB2—Channel B DRAM Rank Boundary Address 2 .................. 100 4.2.15 C1DRB3—Channel B DRAM Rank Boundary Address 3 .................. 101 4.2.16 C1DRA0—Channel B DRAM Rank 0,1 Attribute ............................... 101 4.2.17 C1DRA2—Channel B DRAM Rank 2,3 Attribute ............................... 101 4.2.18 C1DCLKDIS—Channel B DRAM Clock Disable ................................ 101 4.2.19 C1BNKARC—Channel B Bank Architecture ...................................... 101 4.2.20 C1DRT1—Channel B DRAM Timing Register 1 ................................ 102 4.2.21 C1DRC0—Channel B DRAM Controller Mode 0 ............................... 102 4.2.22 C1DRC1—Channel B DRAM Controller Mode 1 ............................... 102 4.2.23 PMCFG—Power Management Configuration .................................... 102 4.2.24 PMSTS—Power Management Status ................................................ 103 4.3 EPBAR Registers—Egress Port Register Summary ......................................... 104 4.3.1 EPESD—EP Element Self Description ............................................... 105 4.3.2 EPLE1D—EP Link Entry 1 Description .............................................. 106 4.3.3 EPLE1A—EP Link Entry 1 Address.................................................... 107 4.3.4 EPLE2D—EP Link Entry 2 Description .............................................. 107 4.3.5 EPLE2A—EP Link Entry 2 Address.................................................... 108 5 Host-PCI Express* Bridge Registers (D1:F0) (Intel ® 82945G/82945GC/82945P/82945PL Only) ................................................................................................................................ 109 5.1 Configuration Register Details (D1:F0) .............................................................. 112 5.1.1 VID1—Vendor Identification (D1:F0) .................................................. 112 5.1.2 DID1—Device Identification (D1:F0) .................................................. 112 5.1.3 PCICMD1—PCI Command (D1:F0) ................................................... 113 5.1.4 PCISTS1—PCI Status (D1:F0) ........................................................... 115 5.1.5 RID1—Revision Identification (D1:F0) ................................................ 116 5.1.6 CC1—Class Code (D1:F0) ................................................................. 116 5.1.7 CL1—Cache Line Size (D1:F0) .......................................................... 117 5.1.8 HDR1—Header Type (D1:F0) ............................................................ 117 5.1.9 PBUSN1—Primary Bus Number (D1:F0) ........................................... 117 5.1.10 SBUSN1—Secondary Bus Number (D1:F0) ...................................... 118 5.1.11 SUBUSN1—Subordinate Bus Number (D1:F0) ................................. 118 5.1.12 IOBASE1—I/O Base Address (D1:F0) ............................................... 119 5.1.13 IOLIMIT1—I/O Limit Address (D1:F0) ................................................ 119 5.1.14 SSTS1—Secondary Status (D1:F0) ................................................... 120 5.1.15 MBASE1—Memory Base Address (D1:F0) ........................................ 121 5.1.16 MLIMIT1—Memory Limit Address (D1:F0) ......................................... 122 5.1.17 PMBASE1—Prefetchable Memory Base Address (D1:F0) ................ 123 5.1.18 PMLIMIT1—Prefetchable Memory Limit Address (D1:F0) ................. 124 5.1.19 CAPPTR1—Capabilities Pointer (D1:F0) ........................................... 124 5.1.20 INTRLINE1—Interrupt Line (D1:F0) ................................................... 125 5.1.21 INTRPIN1—Interrupt Pin (D1:F0) ....................................................... 125 5.1.22 BCTRL1—Bridge Control (D1:F0) ...................................................... 126 5.1.23 PM_CAPID1—Power Management Capabilities (D1:F0) .................. 128 5.1.24 PM_CS1—Power Management Control/Status (D1:F0) .................... 129 5.1.25 SS_CAPID—Subsystem ID and Vendor ID Capabilities (D1:F0) ...... 130 5.1.26 SS—Subsystem ID and Subsystem Vendor ID (D1:F0) .................... 130 5.1.27 MSI_CAPID—Message Signaled Interrupts Capability ID (D1:F0) .... 131 5.1.28 MC—Message Control (D1:F0) .......................................................... 132 5.1.29 MA—Message Address (D1:F0) ......................................................... 133 Intel ® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet 5
- Page 1 and 2: Intel ® 945G/945GZ/945GC/ 945P/945
- Page 3: Contents 1 Introduction ...........
- Page 7 and 8: 6.1.16 DMICESTS—DMI Correctable E
- Page 9 and 10: 9.4.5 SMM Space Decode and Transact
- Page 11 and 12: 11.3 DC Characteristics ...........
- Page 13 and 14: Revision History Rev Description Da
- Page 15 and 16: Intel ® 82945G/82945GZ/82945GC/829
- Page 17 and 18: 1 Introduction Introduction The Int
- Page 19 and 20: Figure 1-2. Intel ® 945GZ/82945GC
- Page 21 and 22: 1.1 Terminology Term Description Ac
- Page 23 and 24: Term Description TOLM Top Of Low Me
- Page 25 and 26: Introduction � Supports four bank
- Page 27 and 28: Introduction 1.4 Graphics (Intel ®
- Page 29 and 30: 1.5 Analog and SDVO Displays (Intel
- Page 31 and 32: 2 Signal Description Signal Descrip
- Page 33 and 34: 2.1 Host Interface Signals Signal D
- Page 35 and 36: Signal Name Type Description HREQ[4
- Page 37 and 38: 2.3 DDR2 DRAM Channel B Interface S
- Page 39 and 40: Signal Description 2.6 Analog Displ
- Page 41 and 42: 2.8 Direct Media Interface (DMI) Si
- Page 43 and 44: 2.10 Power and Ground Name Voltage
- Page 45 and 46: Interface Signal Name I/O System Me
- Page 47 and 48: Interface Signal Name I/O State Dur
- Page 49 and 50: 3 Register Description Register Des
- Page 51 and 52: Register Description Note: A physic
- Page 53 and 54: 3.3 Configuration Mechanisms Regist
4.2.11 C0DRC1—Channel A DRAM Controller Mode 1 ............................... 100<br />
4.2.12 C1DRB0—Channel B DRAM Rank Boundary Address 0 .................. 100<br />
4.2.13 C1DRB1—Channel B DRAM Rank Boundary Address 1 .................. 100<br />
4.2.14 C1DRB2—Channel B DRAM Rank Boundary Address 2 .................. 100<br />
4.2.15 C1DRB3—Channel B DRAM Rank Boundary Address 3 .................. 101<br />
4.2.16 C1DRA0—Channel B DRAM Rank 0,1 Attribute ............................... 101<br />
4.2.17 C1DRA2—Channel B DRAM Rank 2,3 Attribute ............................... 101<br />
4.2.18 C1DCLKDIS—Channel B DRAM Clock Disable ................................ 101<br />
4.2.19 C1BNKARC—Channel B Bank Architecture ...................................... 101<br />
4.2.20 C1DRT1—Channel B DRAM Timing Register 1 ................................ 102<br />
4.2.21 C1DRC0—Channel B DRAM Controller Mode 0 ............................... 102<br />
4.2.22 C1DRC1—Channel B DRAM Controller Mode 1 ............................... 102<br />
4.2.23 PMCFG—Power Management Configuration .................................... 102<br />
4.2.24 PMSTS—Power Management Status ................................................ 103<br />
4.3 EPBAR Registers—Egress Port Register Summary ......................................... 104<br />
4.3.1 EPESD—EP Element Self Description ............................................... 105<br />
4.3.2 EPLE1D—EP Link Entry 1 Description .............................................. 106<br />
4.3.3 EPLE1A—EP Link Entry 1 Address.................................................... 107<br />
4.3.4 EPLE2D—EP Link Entry 2 Description .............................................. 107<br />
4.3.5 EPLE2A—EP Link Entry 2 Address.................................................... 108<br />
5 Host-PCI <strong>Express</strong>* Bridge Registers (D1:F0) (Intel ® 82<strong>945G</strong>/82<strong>945G</strong>C/82<strong>945P</strong>/82<strong>945P</strong>L<br />
Only) ................................................................................................................................ 109<br />
5.1 Configuration Register Details (D1:F0) .............................................................. 112<br />
5.1.1 VID1—Vendor Identification (D1:F0) .................................................. 112<br />
5.1.2 DID1—Device Identification (D1:F0) .................................................. 112<br />
5.1.3 PCICMD1—PCI Command (D1:F0) ................................................... 113<br />
5.1.4 PCISTS1—PCI Status (D1:F0) ........................................................... 115<br />
5.1.5 RID1—Revision Identification (D1:F0) ................................................ 116<br />
5.1.6 CC1—Class Code (D1:F0) ................................................................. 116<br />
5.1.7 CL1—Cache Line Size (D1:F0) .......................................................... 117<br />
5.1.8 HDR1—Header Type (D1:F0) ............................................................ 117<br />
5.1.9 PBUSN1—Primary Bus Number (D1:F0) ........................................... 117<br />
5.1.10 SBUSN1—Secondary Bus Number (D1:F0) ...................................... 118<br />
5.1.11 SUBUSN1—Subordinate Bus Number (D1:F0) ................................. 118<br />
5.1.12 IOBASE1—I/O Base Address (D1:F0) ............................................... 119<br />
5.1.13 IOLIMIT1—I/O Limit Address (D1:F0) ................................................ 119<br />
5.1.14 SSTS1—Secondary Status (D1:F0) ................................................... 120<br />
5.1.15 MBASE1—Memory Base Address (D1:F0) ........................................ 121<br />
5.1.16 MLIMIT1—Memory Limit Address (D1:F0) ......................................... 122<br />
5.1.17 PMBASE1—Prefetchable Memory Base Address (D1:F0) ................ 123<br />
5.1.18 PMLIMIT1—Prefetchable Memory Limit Address (D1:F0) ................. 124<br />
5.1.19 CAPPTR1—Capabilities Pointer (D1:F0) ........................................... 124<br />
5.1.20 INTRLINE1—Interrupt Line (D1:F0) ................................................... 125<br />
5.1.21 INTRPIN1—Interrupt Pin (D1:F0) ....................................................... 125<br />
5.1.22 BCTRL1—Bridge Control (D1:F0) ...................................................... 126<br />
5.1.23 PM_CAPID1—Power Management Capabilities (D1:F0) .................. 128<br />
5.1.24 PM_CS1—Power Management Control/Status (D1:F0) .................... 129<br />
5.1.25 SS_CAPID—Subsystem ID and Vendor ID Capabilities (D1:F0) ...... 130<br />
5.1.26 SS—Subsystem ID and Subsystem Vendor ID (D1:F0) .................... 130<br />
5.1.27 MSI_CAPID—Message Signaled Interrupts Capability ID (D1:F0) .... 131<br />
5.1.28 MC—Message Control (D1:F0) .......................................................... 132<br />
5.1.29 MA—Message Address (D1:F0) ......................................................... 133<br />
Intel ® 82<strong>945G</strong>/82<strong>945G</strong>/82<strong>945G</strong>C GMCH and 82<strong>945P</strong>/82<strong>945P</strong>L MCH Datasheet 5
Change language