Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...
Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ... Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...
Signal Description 2.7 Clocks, Reset, and Miscellaneous Signal Name HCLKP HCLKN GCLKP GCLKN DREFCLKN DREFCLKP Type Description I HCSL I HCSL I HCSL RSTIN# I HVIN PWROK I HVIN EXTTS# I CMOS EXP_EN I CMOS EXP_SLR I CMOS ICH_SYNC# O HVCMOS XORTEST I/O GTL+ ALLZTEST I/O GTL+ Differential Host Clock In: These pins receive a differential host clock from the external clock synthesizer. This clock is used by all of the (G)MCH logic that is in the Host clock domain. Memory domain clocks are also derived from this source. Differential PCI Express* Clock In: These pins receive a differential 100 MHz Serial Reference clock from the external clock synthesizer. This clock is used to generate the clocks necessary for the support of PCI Express. Display PLL Differential Clock In Reset In: When asserted, this signal will asynchronously reset the (G)MCH logic. This signal is connected to the PCIRST# output of the Intel ® ICH7. All PCI Express graphics attach output signals will also tri-state compliant to PCI Express* Specification, Revision 1.0a. This input should have a Schmitt trigger to avoid spurious resets. This signal is required to be 3.3 V tolerant. Power OK: When asserted, PWROK is an indication to the (G)MCH that core power has been stable for at least 10 us. External Thermal Sensor Input: This signal may connect to a precision thermal sensor located on or near the DIMMs. If the system temperature reaches a dangerously high value, then this signal can be used to trigger the start of system thermal management. This signal is activated when an increase in temperature causes a voltage to cross some threshold in the sensor. PCI Express SDVO Concurrent Select 0 = Only SDVO or PCI Express operational 1 = SDVO and PCI Express operating simultaneously via PCI Express port NOTES: For the 82945GZ GMCH and 82945P/82945PL MCH, this signal should be pulled low. PCI Express* Static Lane Reversal/Form Factor Selection: (G)MCH’s PCI Express lane numbers are reversed to differentiate Balanced Technology Extended (BTX) or ATX form factors. 0 = (G)MCH’s PCI Express lane numbers are reversed (BTX Platforms) 1 = Normal operation (ATX Platforms) NOTES: This signal does not apply to the 82945GZ. ICH Sync: This signal is connected to the MCH_SYNCH# signal on the ICH7. XOR Test: This signal is used for Bed of Nails testing by OEMs to execute XOR Chain test. All Z Test: As an input this signal is used for Bed of Nails testing by OEMs to execute XOR Chain test. It is used as an output for XOR chain testing. 40 Intel ® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
2.8 Direct Media Interface (DMI) Signal Name Type Description DMI_RXP[3:0] DMI_RXN[3:0] DMI_TXP[3:0] DMI_TXN[3:0] I/O DMI O DMI Signal Description Direct Media Interface: These signals are receive differential pairs (Rx). Direct Media Interface: These signals are transmit differential pairs (Tx). 2.9 Intel ® Serial DVO (SDVO) Interface (Intel ® 82945G/82945GC/82945GZ GMCH Only) For the 82945G/82945GC GMCH, all but two of the pins in this section are multiplexed with the upper 8 lanes of the PCI Express interface. Signal Name Type Description SDVOB_CLK- O PCIE SDVOB_CLK+ O PCIE SDVOB_RED- O PCIE SDVOB_RED+ O PCIE SDVOB_GREEN- O PCIE SDVOB_GREEN+ O PCIE SDVOB_BLUE- O PCIE SDVOB_BLUE+ O PCIE SDVOC_RED- / SDVOB_ALPHA- SDVOC_RED+ / SDVOB_ALPHA+ O PCIE O PCIE SDVOC_GREEN- O PCIE SDVOC_GREEN+ O PCIE SDVOC_BLUE- O PCIE SDVOC_BLUE+ O PCIE Serial Digital Video Channel B Clock Complement. This signal is multiplexed with EXP_TXN12. Serial Digital Video Channel B Clock. This signal is multiplexed with EXP_TXP12. Serial Digital Video Channel C Red Complement. This signal is multiplexed with EXP_TXN15. Serial Digital Video Channel C Red. This signal is multiplexed with EXP_TXP15. Serial Digital Video Channel B Green Complement. This signal is multiplexed with EXP_TXN14. Serial Digital Video Channel B Green. This signal is multiplexed with EXP_TXP14. Serial Digital Video Channel B Blue Complement. This signal is multiplexed with EXP_TXN13. Serial Digital Video Channel B Blue. This signal is multiplexed with EXP_TXP13. Serial Digital Video Channel C Red Complement Channel B Alpha Complement. This signal is multiplexed with EXP_TXN11. Serial Digital Video Channel C Red Channel B Alpha. This signal is multiplexed with EXP_TXP11. Serial Digital Video Channel C Green Complement. This signal is multiplexed with EXP_TXN10. Serial Digital Video Channel C Green. This signal is multiplexed with EXP_TXP10. Serial Digital Video Channel C Blue Complement. This signal is multiplexed with EXP_TXN9. Serial Digital Video Channel C Blue. This signal is multiplexed with EXP_TXP9. Intel ® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet 41
- Page 1 and 2: Intel ® 945G/945GZ/945GC/ 945P/945
- Page 3 and 4: Contents 1 Introduction ...........
- Page 5 and 6: 4.2.11 C0DRC1—Channel A DRAM Cont
- Page 7 and 8: 6.1.16 DMICESTS—DMI Correctable E
- Page 9 and 10: 9.4.5 SMM Space Decode and Transact
- Page 11 and 12: 11.3 DC Characteristics ...........
- Page 13 and 14: Revision History Rev Description Da
- Page 15 and 16: Intel ® 82945G/82945GZ/82945GC/829
- Page 17 and 18: 1 Introduction Introduction The Int
- Page 19 and 20: Figure 1-2. Intel ® 945GZ/82945GC
- Page 21 and 22: 1.1 Terminology Term Description Ac
- Page 23 and 24: Term Description TOLM Top Of Low Me
- Page 25 and 26: Introduction � Supports four bank
- Page 27 and 28: Introduction 1.4 Graphics (Intel ®
- Page 29 and 30: 1.5 Analog and SDVO Displays (Intel
- Page 31 and 32: 2 Signal Description Signal Descrip
- Page 33 and 34: 2.1 Host Interface Signals Signal D
- Page 35 and 36: Signal Name Type Description HREQ[4
- Page 37 and 38: 2.3 DDR2 DRAM Channel B Interface S
- Page 39: Signal Description 2.6 Analog Displ
- Page 43 and 44: 2.10 Power and Ground Name Voltage
- Page 45 and 46: Interface Signal Name I/O System Me
- Page 47 and 48: Interface Signal Name I/O State Dur
- Page 49 and 50: 3 Register Description Register Des
- Page 51 and 52: Register Description Note: A physic
- Page 53 and 54: 3.3 Configuration Mechanisms Regist
- Page 55 and 56: 3.4 Routing Configuration Accesses
- Page 57 and 58: 3.4.2.2 DMI Configuration Accesses
- Page 59 and 60: Bit Access & Default 10:8 R/W 000b
- Page 61 and 62: Host Bridge/DRAM Controller Registe
- Page 63 and 64: 4.1 Device 0 Configuration Register
- Page 65 and 66: 4.1.4 PCISTS—PCI Status (D0:F0) P
- Page 67 and 68: 4.1.7 MLT—Master Latency Timer (D
- Page 69 and 70: 4.1.12 EPBAR—Egress Port Base Add
- Page 71 and 72: Host Bridge/DRAM Controller Registe
- Page 73 and 74: Host Bridge/DRAM Controller Registe
- Page 75 and 76: Host Bridge/DRAM Controller Registe
- Page 77 and 78: 4.1.19 PAM1—Programmable Attribut
- Page 79 and 80: 4.1.21 PAM3—Programmable Attribut
- Page 81 and 82: 4.1.23 PAM5—Programmable Attribut
- Page 83 and 84: 4.1.25 LAC—Legacy Access Control
- Page 85 and 86: Host Bridge/DRAM Controller Registe
- Page 87 and 88: 4.1.29 ERRSTS—Error Status (D0:F0
- Page 89 and 90: 4.1.31 SKPD—Scratchpad Data (D0:F
2.8 Direct Media Interface (DMI)<br />
Signal Name Type Description<br />
DMI_RXP[3:0]<br />
DMI_RXN[3:0]<br />
DMI_TXP[3:0]<br />
DMI_TXN[3:0]<br />
I/O<br />
DMI<br />
O<br />
DMI<br />
Signal Description<br />
Direct Media Interface: These signals are receive differential pairs (Rx).<br />
Direct Media Interface: These signals are transmit differential pairs (Tx).<br />
2.9 Intel ® Serial DVO (SDVO) Interface (Intel ®<br />
82<strong>945G</strong>/82<strong>945G</strong>C/82<strong>945G</strong>Z GMCH Only)<br />
For the 82<strong>945G</strong>/82<strong>945G</strong>C GMCH, all but two of the pins in this section are multiplexed with the<br />
upper 8 lanes of the PCI <strong>Express</strong> interface.<br />
Signal Name Type Description<br />
SDVOB_CLK- O<br />
PCIE<br />
SDVOB_CLK+ O<br />
PCIE<br />
SDVOB_RED- O<br />
PCIE<br />
SDVOB_RED+ O<br />
PCIE<br />
SDVOB_GREEN- O<br />
PCIE<br />
SDVOB_GREEN+ O<br />
PCIE<br />
SDVOB_BLUE- O<br />
PCIE<br />
SDVOB_BLUE+ O<br />
PCIE<br />
SDVOC_RED- /<br />
SDVOB_ALPHA-<br />
SDVOC_RED+ /<br />
SDVOB_ALPHA+<br />
O<br />
PCIE<br />
O<br />
PCIE<br />
SDVOC_GREEN- O<br />
PCIE<br />
SDVOC_GREEN+ O<br />
PCIE<br />
SDVOC_BLUE- O<br />
PCIE<br />
SDVOC_BLUE+ O<br />
PCIE<br />
Serial Digital Video Channel B Clock Complement. This signal is<br />
multiplexed with EXP_TXN12.<br />
Serial Digital Video Channel B Clock. This signal is multiplexed with<br />
EXP_TXP12.<br />
Serial Digital Video Channel C Red Complement. This signal is<br />
multiplexed with EXP_TXN15.<br />
Serial Digital Video Channel C Red. This signal is multiplexed with<br />
EXP_TXP15.<br />
Serial Digital Video Channel B Green Complement. This signal is<br />
multiplexed with EXP_TXN14.<br />
Serial Digital Video Channel B Green. This signal is multiplexed with<br />
EXP_TXP14.<br />
Serial Digital Video Channel B Blue Complement. This signal is<br />
multiplexed with EXP_TXN13.<br />
Serial Digital Video Channel B Blue. This signal is multiplexed with<br />
EXP_TXP13.<br />
Serial Digital Video Channel C Red Complement Channel B Alpha<br />
Complement. This signal is multiplexed with EXP_TXN11.<br />
Serial Digital Video Channel C Red Channel B Alpha. This signal is<br />
multiplexed with EXP_TXP11.<br />
Serial Digital Video Channel C Green Complement. This signal is<br />
multiplexed with EXP_TXN10.<br />
Serial Digital Video Channel C Green. This signal is multiplexed with<br />
EXP_TXP10.<br />
Serial Digital Video Channel C Blue Complement. This signal is<br />
multiplexed with EXP_TXN9.<br />
Serial Digital Video Channel C Blue. This signal is multiplexed with<br />
EXP_TXP9.<br />
Intel ® 82<strong>945G</strong>/82<strong>945G</strong>/82<strong>945G</strong>C GMCH and 82<strong>945P</strong>/82<strong>945P</strong>L MCH Datasheet 41