Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

Signal Description
2.7 Clocks, Reset, and Miscellaneous
Signal
Name
HCLKP
HCLKN
GCLKP
GCLKN
DREFCLKN
DREFCLKP
Type Description
I
HCSL
I
HCSL
I
HCSL
RSTIN# I
HVIN
PWROK I
HVIN
EXTTS# I
CMOS
EXP_EN I
CMOS
EXP_SLR I
CMOS
ICH_SYNC# O
HVCMOS
XORTEST I/O
GTL+
ALLZTEST I/O
GTL+
Differential Host Clock In: These pins receive a differential host clock from
the external clock synthesizer. This clock is used by all of the (G)MCH logic
that is in the Host clock domain. Memory domain clocks are also derived
from this source.
Differential PCI Express* Clock In: These pins receive a differential
100 MHz Serial Reference clock from the external clock synthesizer. This
clock is used to generate the clocks necessary for the support of PCI
Express.
Display PLL Differential Clock In
Reset In: When asserted, this signal will asynchronously reset the (G)MCH
logic. This signal is connected to the PCIRST# output of the Intel ® ICH7. All
PCI Express graphics attach output signals will also tri-state compliant to
PCI Express* Specification, Revision 1.0a.
This input should have a Schmitt trigger to avoid spurious resets.
This signal is required to be 3.3 V tolerant.
Power OK: When asserted, PWROK is an indication to the (G)MCH that
core power has been stable for at least 10 us.
External Thermal Sensor Input: This signal may connect to a precision
thermal sensor located on or near the DIMMs. If the system temperature
reaches a dangerously high value, then this signal can be used to trigger
the start of system thermal management. This signal is activated when an
increase in temperature causes a voltage to cross some threshold in the
sensor.
PCI Express SDVO Concurrent Select
0 = Only SDVO or PCI Express operational
1 = SDVO and PCI Express operating simultaneously via PCI Express
port
NOTES: For the 82945GZ GMCH and 82945P/82945PL MCH, this signal
should be pulled low.
PCI Express* Static Lane Reversal/Form Factor Selection: (G)MCH’s
PCI Express lane numbers are reversed to differentiate Balanced
Technology Extended (BTX) or ATX form factors.
0 = (G)MCH’s PCI Express lane numbers are reversed (BTX Platforms)
1 = Normal operation (ATX Platforms)
NOTES: This signal does not apply to the 82945GZ.
ICH Sync: This signal is connected to the MCH_SYNCH# signal on the
ICH7.
XOR Test: This signal is used for Bed of Nails testing by OEMs to execute
XOR Chain test.
All Z Test: As an input this signal is used for Bed of Nails testing by OEMs
to execute XOR Chain test. It is used as an output for XOR chain testing.
40 Intel ® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet