Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

Signal Description
2.2 DDR2 DRAM Channel A Interface
Signal Name Type Description
SCLK_A[5:0] O
SSTL-1.8
SCLK_A[5:0]# O
SSTL-1.8
SCS_A[3:0]# O
SSTL-1.8
SMA_A[13:0] O
SSTL-1.8
SBS_A[2:0] O
SSTL-1.8
SRAS_A# O
SSTL-1.8
SCAS_A# O
SSTL-1.8
SWE_A# O
SSTL-1.8
SDQ_A[63:0] I/O
SSTL-1.8
2x
SDM_A[7:0] O
SSTL-1.8
2X
SDQS_A[7:0] I/O
SSTL-1.8
2x
SDQS_A[7:0]# I/O
SSTL-1.8
2x
SCKE_A[3:0] O
SSTL-1.8
SODT_A[3:0] O
SSTL-1.8
SDRAM Differential Clock: (3 per DIMM). SCLK_Ax and its complement
SCLK_Ax# signal make a differential clock pair output. The crossing of the
positive edge of SCLK_Ax and the negative edge of its complement
SCLK_Ax# are used to sample the command and control signals on the
SDRAM.
SDRAM Complementary Differential Clock: (3 per DIMM). These are the
complementary Differential DDR2 Clock signals.
Chip Select: (1 per Rank). These signals select particular SDRAM
components during the active state. There is one chip select for each
SDRAM rank.
Memory Address: These signals are used to provide the multiplexed row
and column address to the SDRAM.
Bank Select: These signals define which banks are selected within each
SDRAM rank.
DDR2: 1-Gb technology is 8 banks.
Row Address Strobe: This signal is used with SCAS_A# and SWE_A#
(along with SCS_A#) to define the SDRAM commands.
Column Address Strobe: This signal is used with SRAS_A# and SWE_A#
(along with SCS_A#) to define the SDRAM commands.
Write Enable: This signal is used with SCAS_A# and SRAS_A# (along with
SCS_A#) to define the SDRAM commands.
Data Lines: The SDQ_A[63:0] signals interface to the SDRAM data bus.
Data Mask: When activated during writes, the corresponding data groups in
the SDRAM are masked. There is one SDM_Ax bit for every data byte lane.
Data Strobes: For DDR2, SDQS_Ax and its complement SDQS_Ax# signal
make up a differential strobe pair. The data is captured at the crossing point
of SDQS_Ax and its complement SDQS_Ax# during read and write
transactions.
Data Strobe Complements: These are the complementary DDR2 strobe
signals.
Clock Enable: (1 per Rank). SCKE_Ax is used to initialize the SDRAMs
during power-up, to power-down SDRAM ranks, and to place all SDRAM
ranks into and out of self-refresh during Suspend-to-RAM.
On Die Termination: Active On-die Termination Control signals for DDR2
devices.
36 Intel ® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet