Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...
Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ... Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...
Testability 13 Testability In the (G)MCH, testability for Automated Test Equipment (ATE) board level testing has been implemented as an XOR chain. An XOR-tree is a chain of XOR gates each with one input pin connected to it. 13.1 Complimentary Pins Table 13-1 contains pins that must remain complimentary while performing XOR testing. The first and third column contain the pin and its compliment. The second and fourth column specify which chain the associated pins are on. Table 13-1. Complimentary Pins to Drive Complimentary Pin XOR Chain Complimentary Pin XOR Chain SDQS_A0 Not in XOR Chain SDQS_A0# 4 SDQS_A1 Not in XOR Chain SDQS_A1# 4 SDQS_A2 Not in XOR Chain SDQS_A2# 4 SDQS A3 Not in XOR Chain SDQS_A3# 4 SDQS_A4 Not in XOR Chain SDQS_A4# 4 SDQS_A5 Not in XOR Chain SDQS_A5# 4 SDQS_A6 Not in XOR Chain SDQS_A6# 4 SDQS_A7 Not in XOR Chain SDQS_A7# 4 SDQS_B0 Not in XOR Chain SDQS_B0# 5 SDQS_B1 Not in XOR Chain SDQS_B1# 5 SDQS_B2 Not in XOR Chain SDQS_B2# 5 SDQS_B3 Not in XOR Chain SDQS_B3# 5 SDQS_B4 Not in XOR Chain SDQS_B4# 5 SDQS_B5 Not in XOR Chain SDQS_B5# 5 SDQS_B6 Not in XOR Chain SDQS_B6# 5 SDQS_B7 Not in XOR Chain SDQS_B7# 5 308 Intel ® 82945G/82945GZ GMCH and 82945P/82945PL MCH Datasheet
13.2 XOR Test Mode Initialization Testability XOR test mode can be entered by pulling a Reserved ball (ball V30) and XORTEST (ball H20) low through the de-assertion of external reset (RSTIN# at ball AJ12). It was intended that no clocks should be required to enter this test mode; however, it is recommended that customers use the following sequence. On power up, hold PWROK (ball AJ9), RSTIN# (ball AJ12), and a Reserved ball (ball V30) low and start external clocks. After a few clock cycles, pull PWROK high. After ~3–4 clocks, deassert RSTIN# (pull it high). Release the Reserved ball (ball V30) and XORTEST. No external drive. Allow the clocks to run for an additional 32 clocks. Begin testing the XOR chains. Refer to Figure 13-1. Figure 13-1. XOR Test Mode Initialization Cycles PWROK XORTEST Reserved Ball V30 RSTIN# Start XOR testing ~3-4 Clocks Don’t Care Don’t Care 32 clocks XOR_Chain_Tim Intel ® 82945G/82945GZ GMCH and 82945P/82945PL MCH Datasheet 309
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13.2 XOR Test Mode Initialization<br />
Testability<br />
XOR test mode can be entered by pulling a Reserved ball (ball V30) and XORTEST (ball H20)<br />
low through the de-assertion of external reset (RSTIN# at ball AJ12). It was intended that no<br />
clocks should be required to enter this test mode; however, it is recommended that customers use<br />
the following sequence.<br />
On power up, hold PWROK (ball AJ9), RSTIN# (ball AJ12), and a Reserved ball (ball V30) low<br />
and start external clocks. After a few clock cycles, pull PWROK high. After ~3–4 clocks, deassert<br />
RSTIN# (pull it high). Release the Reserved ball (ball V30) and XORTEST. No external<br />
drive. Allow the clocks to run for an additional 32 clocks. Begin testing the XOR chains. Refer to<br />
Figure 13-1.<br />
Figure 13-1. XOR Test Mode Initialization Cycles<br />
PWROK<br />
XORTEST<br />
Reserved Ball V30<br />
RSTIN#<br />
Start XOR testing<br />
~3-4 Clocks<br />
Don’t Care<br />
Don’t Care<br />
32 clocks<br />
XOR_Chain_Tim<br />
Intel ® 82<strong>945G</strong>/82<strong>945G</strong>Z GMCH and 82<strong>945P</strong>/82<strong>945P</strong>L MCH Datasheet 309
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