Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

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Testability 13 Testability In the (G)MCH, testability for Automated Test Equipment (ATE) board level testing has been implemented as an XOR chain. An XOR-tree is a chain of XOR gates each with one input pin connected to it. 13.1 Complimentary Pins Table 13-1 contains pins that must remain complimentary while performing XOR testing. The first and third column contain the pin and its compliment. The second and fourth column specify which chain the associated pins are on. Table 13-1. Complimentary Pins to Drive Complimentary Pin XOR Chain Complimentary Pin XOR Chain SDQS_A0 Not in XOR Chain SDQS_A0# 4 SDQS_A1 Not in XOR Chain SDQS_A1# 4 SDQS_A2 Not in XOR Chain SDQS_A2# 4 SDQS A3 Not in XOR Chain SDQS_A3# 4 SDQS_A4 Not in XOR Chain SDQS_A4# 4 SDQS_A5 Not in XOR Chain SDQS_A5# 4 SDQS_A6 Not in XOR Chain SDQS_A6# 4 SDQS_A7 Not in XOR Chain SDQS_A7# 4 SDQS_B0 Not in XOR Chain SDQS_B0# 5 SDQS_B1 Not in XOR Chain SDQS_B1# 5 SDQS_B2 Not in XOR Chain SDQS_B2# 5 SDQS_B3 Not in XOR Chain SDQS_B3# 5 SDQS_B4 Not in XOR Chain SDQS_B4# 5 SDQS_B5 Not in XOR Chain SDQS_B5# 5 SDQS_B6 Not in XOR Chain SDQS_B6# 5 SDQS_B7 Not in XOR Chain SDQS_B7# 5 308 Intel ® 82945G/82945GZ GMCH and 82945P/82945PL MCH Datasheet
13.2 XOR Test Mode Initialization Testability XOR test mode can be entered by pulling a Reserved ball (ball V30) and XORTEST (ball H20) low through the de-assertion of external reset (RSTIN# at ball AJ12). It was intended that no clocks should be required to enter this test mode; however, it is recommended that customers use the following sequence. On power up, hold PWROK (ball AJ9), RSTIN# (ball AJ12), and a Reserved ball (ball V30) low and start external clocks. After a few clock cycles, pull PWROK high. After ~3–4 clocks, deassert RSTIN# (pull it high). Release the Reserved ball (ball V30) and XORTEST. No external drive. Allow the clocks to run for an additional 32 clocks. Begin testing the XOR chains. Refer to Figure 13-1. Figure 13-1. XOR Test Mode Initialization Cycles PWROK XORTEST Reserved Ball V30 RSTIN# Start XOR testing ~3-4 Clocks Don’t Care Don’t Care 32 clocks XOR_Chain_Tim Intel ® 82945G/82945GZ GMCH and 82945P/82945PL MCH Datasheet 309
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Intel ® 945G/945GZ/945GC/ 945P/945
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Contents 1 Introduction ...........
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4.2.11 C0DRC1—Channel A DRAM Cont
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6.1.16 DMICESTS—DMI Correctable E
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9.4.5 SMM Space Decode and Transact
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11.3 DC Characteristics ...........
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Revision History Rev Description Da
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Intel ® 82945G/82945GZ/82945GC/829
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1 Introduction Introduction The Int
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Figure 1-2. Intel ® 945GZ/82945GC
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1.1 Terminology Term Description Ac
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Term Description TOLM Top Of Low Me
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Introduction � Supports four bank
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Introduction 1.4 Graphics (Intel ®
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1.5 Analog and SDVO Displays (Intel
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2 Signal Description Signal Descrip
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2.1 Host Interface Signals Signal D
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Signal Name Type Description HREQ[4
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2.3 DDR2 DRAM Channel B Interface S
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Signal Description 2.6 Analog Displ
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2.8 Direct Media Interface (DMI) Si
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2.10 Power and Ground Name Voltage
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Interface Signal Name I/O System Me
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Interface Signal Name I/O State Dur
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3 Register Description Register Des
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Register Description Note: A physic
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3.3 Configuration Mechanisms Regist
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3.4 Routing Configuration Accesses
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3.4.2.2 DMI Configuration Accesses
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Bit Access & Default 10:8 R/W 000b
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Host Bridge/DRAM Controller Registe
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4.1 Device 0 Configuration Register
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4.1.4 PCISTS—PCI Status (D0:F0) P
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4.1.7 MLT—Master Latency Timer (D
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4.1.12 EPBAR—Egress Port Base Add
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4.1.19 PAM1—Programmable Attribut
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4.1.25 LAC—Legacy Access Control
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4.1.29 ERRSTS—Error Status (D0:F0
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4.1.31 SKPD—Scratchpad Data (D0:F
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4.2.7 C0DCLKDIS—Channel A DRAM Cl
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4.2.9 C0DRT1—Channel A DRAM Timin
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Bit Access & Default 6:4 R/W 000b 3
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4.2.24 PMSTS—Power Management Sta
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4.3.1 EPESD—EP Element Self Descr
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4.3.3 EPLE1A—EP Link Entry 1 Addr
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Host-PCI Express* Bridge Registers
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Address Offset Host-PCI Express* Br
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5.1.3 PCICMD1—PCI Command (D1:F0)
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5.1.4 PCISTS1—PCI Status (D1:F0)
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5.1.7 CL1—Cache Line Size (D1:F0)
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5.1.12 IOBASE1—I/O Base Address (
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5.1.15 MBASE1—Memory Base Address
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5.1.20 INTRLINE1—Interrupt Line (
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Bit Access & Default 2 R/W 0b 1 R/W
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5.1.29 MA—Message Address (D1:F0)
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5.1.33 DCAP—Device Capabilities (
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5.1.35 DSTS—Device Status (D1:F0)
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5.1.37 LCTL—Link Control (D1:F0)
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5.1.39 SLOTCAP—Slot Capabilities
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5.1.41 SLOTSTS—Slot Status (D1:F0
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5.1.43 RSTS—Root Status (D1:F0) P
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5.1.56 ESD—Element Self Descripti
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5.1.61 CESTS—Correctable Error St
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Direct Media Interface (DMI) RCRB 6
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6.1.3 DMIPVCCAP2—DMI Port VC Capa
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6.1.6 DMIVC0RCTL—DMI VC0 Resource
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6.1.9 DMIVC1RCTL—DMI VC1 Resource
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6.1.13 DMILSTS—DMI Link Status MM
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6.1.15 DMIUEMSK—DMI Uncorrectable
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Integrated Graphics Device (D2:F0)
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7.1.4 PCISTS2—PCI Status (D2:F0)
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7.1.7 CLS—Cache Line Size (D2:F0)
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7.1.11 IOBAR—I/O Base Address (D2
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7.1.20 MINGNT—Minimum Grant (D2:F
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8.1.3 PCICMD2—PCI Command (D2:F1)
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8.1.5 RID2—Revision Identificatio
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8.2 Device 2 - PCI I/O Registers In
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9 System Address Map System Address
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Figure 9-1. System Address Ranges 4
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Compatible SMRAM Address Range (A_0
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9.2 Main Memory Address Range (1 MB
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9.3 PCI Memory Address Range (TOLUD
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9.3.6 PCI Express* Graphics Attach
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9.4.1 SMM Space Definition System A
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9.4.5 SMM Space Decode and Transact
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9.4.12 Legacy VGA and I/O Range Dec
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10 Functional Description This chap
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Interleaved Mode Functional Descrip
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667 MHz (PC 5300) (82945G/82945GC/8
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10.2.2.2 System Memory Supported Co
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Functional Description Table 10-5.
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10.3 PCI Express* (Intel ® 82945G/
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Figure 10-2. SDVO Conceptual Block
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Figure 10-3. Concurrent SDVO / PCI
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10.5 Integrated Graphics Device (In
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10.5.3 4X Faster Setup Engine Funct
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10.5.4 Texture Engine Functional De
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10.5.4.8 Pixel Shader Functional De
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Functional Description to determine
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10.5.6 2D Engine Functional Descrip
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10.5.8.1 Cursor Plane Functional De
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Functional Description device is in
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10.6.2 Digital Display Interface Fu
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Page 261 and 262: 11 Electrical Characteristics Elect
Page 263 and 264: 11.1.1 Power Characteristics Table
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Page 267 and 268: 11.3 DC Characteristics Table 11-5.
Page 269 and 270: Symbol Signal Group Electrical Char
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Page 273 and 274: Ballout and Package Information Fig
Page 275 and 276: 12.2 Ballout Table Ballout and Pack
Page 277 and 278: Ballout and Package Information EXP
Page 279 and 280: Ballout and Package Information HA2
Page 281 and 282: Ballout and Package Information HD6
Page 283 and 284: Ballout and Package Information RSV
Page 285 and 286: Ballout and Package Information SDM
Page 287 and 288: Ballout and Package Information SDQ
Page 289 and 290: Ballout and Package Information SDQ
Page 291 and 292: Ballout and Package Information VCC
Page 297 and 298: Ballout and Package Information VSS
Page 305 and 306: 12.3 Package § Ballout and Package
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Page 311 and 312: 13.4 XOR Chains Testability Table 1
Page 313 and 314: Table 13-5. XOR Chain 2 Pin Count B
Page 315 and 316: Table 13-8. XOR Chain 5 Pin Count B
Page 317 and 318: Table 13-11. XOR Chain 8 Pin Count
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Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

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