Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

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Ballout and Package Information SDQ_A28 SDQ_A28 SDQ_A28 AP17 SDQ_A29 SDQ_A29 SDQ_A29 AR17 SDQ_A30 SDQ_A30 SDQ_A30 AP20 SDQ_A31 SDQ_A31 SDQ_A31 AT20 SDQ_A32 SDQ_A32 SDQ_A32 AP32 SDQ_A33 SDQ_A33 SDQ_A33 AV34 SDQ_A34 SDQ_A34 SDQ_A34 AV38 SDQ_A35 SDQ_A35 SDQ_A35 AU39 SDQ_A36 SDQ_A36 SDQ_A36 AV32 SDQ_A37 SDQ_A37 SDQ_A37 AT32 SDQ_A38 SDQ_A38 SDQ_A38 AR34 SDQ_A39 SDQ_A39 SDQ_A39 AU37 SDQ_A40 SDQ_A40 SDQ_A40 AR41 SDQ_A41 SDQ_A41 SDQ_A41 AR42 SDQ_A42 SDQ_A42 SDQ_A42 AN43 SDQ_A43 SDQ_A43 SDQ_A43 AM40 SDQ_A44 SDQ_A44 SDQ_A44 AU41 SDQ_A45 SDQ_A45 SDQ_A45 AU42 SDQ_A46 SDQ_A46 SDQ_A46 AP41 SDQ_A47 SDQ_A47 SDQ_A47 AN40 SDQ_A48 SDQ_A48 SDQ_A48 AL41 SDQ_A49 SDQ_A49 SDQ_A49 AL42 SDQ_A50 SDQ_A50 SDQ_A50 AF39 SDQ_A51 SDQ_A51 SDQ_A51 AE40 SDQ_A52 SDQ_A52 SDQ_A52 AM41 SDQ_A53 SDQ_A53 SDQ_A53 AM42 SDQ_A54 SDQ_A54 SDQ_A54 AF41 SDQ_A55 SDQ_A55 SDQ_A55 AF42 SDQ_A56 SDQ_A56 SDQ_A56 AD40 SDQ_A57 SDQ_A57 SDQ_A57 AD43 SDQ_A58 SDQ_A58 SDQ_A58 AA39 SDQ_A59 SDQ_A59 SDQ_A59 AA40 SDQ_A60 SDQ_A60 SDQ_A60 AE42 SDQ_A61 SDQ_A61 SDQ_A61 AE41 SDQ_A62 SDQ_A62 SDQ_A62 AB41 SDQ_A63 SDQ_A63 SDQ_A63 AB42 SDQ_B0 SDQ_B0 SDQ_B0 AL6 SDQ_B1 SDQ_B1 SDQ_B1 AL8 SDQ_B2 SDQ_B2 SDQ_B2 AP8 SDQ_B3 SDQ_B3 SDQ_B3 AP9 SDQ_B4 SDQ_B4 SDQ_B4 AJ11 286 Intel ® 82945G/82945GZ GMCH and 82945P/82945PL MCH Datasheet
Ballout and Package Information SDQ_B5 SDQ_B5 SDQ_B5 AL9 SDQ_B6 SDQ_B6 SDQ_B6 AM10 SDQ_B7 SDQ_B7 SDQ_B7 AP6 SDQ_B8 SDQ_B8 SDQ_B8 AU7 SDQ_B9 SDQ_B9 SDQ_B9 AV6 SDQ_B10 SDQ_B10 SDQ_B10 AV12 SDQ_B11 SDQ_B11 SDQ_B11 AM11 SDQ_B12 SDQ_B12 SDQ_B12 AR5 SDQ_B13 SDQ_B13 SDQ_B13 AR7 SDQ_B14 SDQ_B14 SDQ_B14 AR12 SDQ_B15 SDQ_B15 SDQ_B15 AR10 SDQ_B16 SDQ_B16 SDQ_B16 AM15 SDQ_B17 SDQ_B17 SDQ_B17 AM13 SDQ_B18 SDQ_B18 SDQ_B18 AV15 SDQ_B19 SDQ_B19 SDQ_B19 AM17 SDQ_B20 SDQ_B20 SDQ_B20 AN12 SDQ_B21 SDQ_B21 SDQ_B21 AR13 SDQ_B22 SDQ_B22 SDQ_B22 AP15 SDQ_B23 SDQ_B23 SDQ_B23 AT15 SDQ_B24 SDQ_B24 SDQ_B24 AM24 SDQ_B25 SDQ_B25 SDQ_B25 AM23 SDQ_B26 SDQ_B26 SDQ_B26 AV24 SDQ_B27 SDQ_B27 SDQ_B27 AM26 SDQ_B28 SDQ_B28 SDQ_B28 AP21 SDQ_B29 SDQ_B29 SDQ_B29 AR21 SDQ_B30 SDQ_B30 SDQ_B30 AP24 SDQ_B31 SDQ_B31 SDQ_B31 AT24 SDQ_B32 SDQ_B32 SDQ_B32 AU27 SDQ_B33 SDQ_B33 SDQ_B33 AN29 SDQ_B34 SDQ_B34 SDQ_B34 AR31 SDQ_B35 SDQ_B35 SDQ_B35 AM31 SDQ_B36 SDQ_B36 SDQ_B36 AP27 SDQ_B37 SDQ_B37 SDQ_B37 AR27 SDQ_B38 SDQ_B38 SDQ_B38 AP31 SDQ_B39 SDQ_B39 SDQ_B39 AU31 SDQ_B40 SDQ_B40 SDQ_B40 AP35 SDQ_B41 SDQ_B41 SDQ_B41 AP37 SDQ_B42 SDQ_B42 SDQ_B42 AN32 SDQ_B43 SDQ_B43 SDQ_B43 AL35 SDQ_B44 SDQ_B44 SDQ_B44 AR35 SDQ_B45 SDQ_B45 SDQ_B45 AU38 Intel ® 82945G/82945GZ GMCH and 82945P/82945PL MCH Datasheet 287
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Intel ® 945G/945GZ/945GC/ 945P/945
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Contents 1 Introduction ...........
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4.2.11 C0DRC1—Channel A DRAM Cont
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6.1.16 DMICESTS—DMI Correctable E
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9.4.5 SMM Space Decode and Transact
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11.3 DC Characteristics ...........
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Revision History Rev Description Da
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Intel ® 82945G/82945GZ/82945GC/829
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1 Introduction Introduction The Int
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Figure 1-2. Intel ® 945GZ/82945GC
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1.1 Terminology Term Description Ac
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Term Description TOLM Top Of Low Me
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Introduction � Supports four bank
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Introduction 1.4 Graphics (Intel ®
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1.5 Analog and SDVO Displays (Intel
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2 Signal Description Signal Descrip
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2.1 Host Interface Signals Signal D
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Signal Name Type Description HREQ[4
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2.3 DDR2 DRAM Channel B Interface S
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Signal Description 2.6 Analog Displ
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2.8 Direct Media Interface (DMI) Si
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2.10 Power and Ground Name Voltage
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Interface Signal Name I/O System Me
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Interface Signal Name I/O State Dur
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3 Register Description Register Des
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Register Description Note: A physic
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3.3 Configuration Mechanisms Regist
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3.4 Routing Configuration Accesses
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3.4.2.2 DMI Configuration Accesses
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Bit Access & Default 10:8 R/W 000b
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Host Bridge/DRAM Controller Registe
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4.1 Device 0 Configuration Register
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4.1.4 PCISTS—PCI Status (D0:F0) P
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4.1.7 MLT—Master Latency Timer (D
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4.1.12 EPBAR—Egress Port Base Add
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4.1.19 PAM1—Programmable Attribut
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4.1.25 LAC—Legacy Access Control
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4.1.29 ERRSTS—Error Status (D0:F0
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4.1.31 SKPD—Scratchpad Data (D0:F
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4.2.7 C0DCLKDIS—Channel A DRAM Cl
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4.2.9 C0DRT1—Channel A DRAM Timin
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Bit Access & Default 6:4 R/W 000b 3
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4.2.24 PMSTS—Power Management Sta
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4.3.1 EPESD—EP Element Self Descr
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4.3.3 EPLE1A—EP Link Entry 1 Addr
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Host-PCI Express* Bridge Registers
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Address Offset Host-PCI Express* Br
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5.1.3 PCICMD1—PCI Command (D1:F0)
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5.1.4 PCISTS1—PCI Status (D1:F0)
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5.1.7 CL1—Cache Line Size (D1:F0)
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5.1.12 IOBASE1—I/O Base Address (
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5.1.15 MBASE1—Memory Base Address
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5.1.20 INTRLINE1—Interrupt Line (
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Bit Access & Default 2 R/W 0b 1 R/W
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5.1.29 MA—Message Address (D1:F0)
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5.1.33 DCAP—Device Capabilities (
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5.1.35 DSTS—Device Status (D1:F0)
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5.1.37 LCTL—Link Control (D1:F0)
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5.1.39 SLOTCAP—Slot Capabilities
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5.1.41 SLOTSTS—Slot Status (D1:F0
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5.1.43 RSTS—Root Status (D1:F0) P
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5.1.56 ESD—Element Self Descripti
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5.1.61 CESTS—Correctable Error St
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Direct Media Interface (DMI) RCRB 6
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6.1.3 DMIPVCCAP2—DMI Port VC Capa
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6.1.6 DMIVC0RCTL—DMI VC0 Resource
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6.1.9 DMIVC1RCTL—DMI VC1 Resource
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6.1.13 DMILSTS—DMI Link Status MM
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6.1.15 DMIUEMSK—DMI Uncorrectable
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Integrated Graphics Device (D2:F0)
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7.1.4 PCISTS2—PCI Status (D2:F0)
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7.1.7 CLS—Cache Line Size (D2:F0)
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7.1.11 IOBAR—I/O Base Address (D2
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7.1.20 MINGNT—Minimum Grant (D2:F
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8.1.3 PCICMD2—PCI Command (D2:F1)
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8.1.5 RID2—Revision Identificatio
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8.2 Device 2 - PCI I/O Registers In
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9 System Address Map System Address
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Figure 9-1. System Address Ranges 4
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Compatible SMRAM Address Range (A_0
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9.2 Main Memory Address Range (1 MB
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9.3 PCI Memory Address Range (TOLUD
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9.3.6 PCI Express* Graphics Attach
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9.4.1 SMM Space Definition System A
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9.4.5 SMM Space Decode and Transact
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9.4.12 Legacy VGA and I/O Range Dec
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10 Functional Description This chap
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Interleaved Mode Functional Descrip
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667 MHz (PC 5300) (82945G/82945GC/8
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10.2.2.2 System Memory Supported Co
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Functional Description Table 10-5.
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10.3 PCI Express* (Intel ® 82945G/
Page 235 and 236: Figure 10-2. SDVO Conceptual Block
Page 237 and 238: Figure 10-3. Concurrent SDVO / PCI
Page 239 and 240: 10.5 Integrated Graphics Device (In
Page 241 and 242: 10.5.3 4X Faster Setup Engine Funct
Page 243 and 244: 10.5.4 Texture Engine Functional De
Page 245 and 246: 10.5.4.8 Pixel Shader Functional De
Page 247 and 248: Functional Description to determine
Page 249 and 250: 10.5.6 2D Engine Functional Descrip
Page 251 and 252: 10.5.8.1 Cursor Plane Functional De
Page 253 and 254: Functional Description device is in
Page 255 and 256: 10.6.2 Digital Display Interface Fu
Page 257 and 258: 10.6.2.1.5 Control Bus Functional D
Page 259 and 260: Figure 10-7 illustrates the various
Page 261 and 262: 11 Electrical Characteristics Elect
Page 263 and 264: 11.1.1 Power Characteristics Table
Page 265 and 266: Signal Group Electrical Characteris
Page 267 and 268: 11.3 DC Characteristics Table 11-5.
Page 269 and 270: Symbol Signal Group Electrical Char
Page 271 and 272: Ballout and Package Information 12
Page 273 and 274: Ballout and Package Information Fig
Page 275 and 276: 12.2 Ballout Table Ballout and Pack
Page 277 and 278: Ballout and Package Information EXP
Page 279 and 280: Ballout and Package Information HA2
Page 281 and 282: Ballout and Package Information HD6
Page 283 and 284: Ballout and Package Information RSV
Page 285: Ballout and Package Information SDM
Page 289 and 290: Ballout and Package Information SDQ
Page 291 and 292: Ballout and Package Information VCC
Page 297 and 298: Ballout and Package Information VSS
Page 305 and 306: 12.3 Package § Ballout and Package
Page 307 and 308: Ballout and Package Information Int
Page 309 and 310: 13.2 XOR Test Mode Initialization T
Page 311 and 312: 13.4 XOR Chains Testability Table 1
Page 313 and 314: Table 13-5. XOR Chain 2 Pin Count B
Page 315 and 316: Table 13-8. XOR Chain 5 Pin Count B
Page 317 and 318: Table 13-11. XOR Chain 8 Pin Count
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Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

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