Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

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Ballout and Package Information Figure 12-3. Intel ® 82945G GMCH Ballout Diagram (Top View – Columns 15–1) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BC VCCSM SDQ_A22 VSS SDQ_A14 VSS NC NC BC BB VSS SCKE_B3 SDQ_A19 VSS SDM_A2 SDQ_A21 SDQ_A11 VSS SCLK_A1# SDQS_A1# VSS NC NC BB BA SCKE_B0 SCKE_B2 SDQ_A18 SDQS_A2# SDQ_A20 SDQ_A10 SCLK_A4# VSS SDQS_A1 NC BA AY RSV SDQ_A23 SDQS_A2 SDQ_A17 SDQ_A15 SCLK_A4 SCLK_A1 SDQ_A9 SDM_A1 VSS AY AW VCCSM VCCSM SDQ_A16 VSS SCLK_B1# SDM_B1 SDQ_A13 SDQ_A8 NC AW AV SDQ_B18 SDQS_B2 SDQ_B10 VSS SCLK_B1 SDQS_B1 SDQ_B9 SDQ_A3 VSS SDQ_A12 AV AU VSS VSS VSS SCLK_B4 VSS SDQ_B8 VSS SDQ_A6 SDQS_A0 SDQ_A2 SDQ_A7 AU AT SDQ_B23 SDQS_B2# VSS SCLK_B4# AT AR VSS SDQ_B21 SDQ_B14 SDQ_B15 SDQS_B1# SDQ_B13 VSS SDQ_B12 SDM_A0 SDQS_A0# VSS AR AP SDQ_B22 SDM_B2 VSS VSS SDQ_B3 SDQ_B2 VSS SDQ_B7 VSS SDQ_A5 SDQ_A0 SDQ_A1 AP AN VSS VSS SDQ_B20 VSS VSS SDQ_A4 AN AM SDQ_B16 SDQ_B17 SDQ_B11 SDQ_B6 VSS SDQS_B0 VSS SDQS_B0# VSS SMVREF0 SOCOMP1 SMVREF1 AM AL VSS VSS VSS SDM_B0 VSS SDQ_B5 SDQ_B1 VSS SDQ_B0 SRCOMP0 VSS VSS VSS AL AK VCC VCC VCC VCC VCC AK AJ VCC VCC VCC RSTIN# SDQ_B4 VSS PWROK SOCOMP0 VSS SRCOMP1 VCC AJ AH VCC VCC VCC AH AG VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC AG AF VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VSS VSS VSS VSS AF AE VCC_EXP VCC_EXP VCC_EXP AE AD VCC VCC VSS VCC_EXP VSS VCC_EXP VSS VCC_EXP VSS VCC_EXP VCC_EXP VCC_EXP VCC_EXP VCC_EXP AD AC VCC VSS VCC_EXP 274 EXP_ COMPO EXP_ COMPI VSS DMI_RXP3 DMI_RXN3 VSS VCC_EXP VCC_EXP DMI_TXN3 VSS VSS AC AB DMI_TXP3 VSS DMI_TXN1 AB AA VCC VSS VCC_EXP VSS VSS DMI_RXN1 DMI_RXP1 VSS DMI_RXN2 DMI_RXP2 VCC_EXP DMI_TXN2 VSS DMI_TXP1 AA Y VCC VSS VCC_EXP VSS EXP_ RXN15 EXP_ RXP15 VSS DMI_RXN0 DMI_RXP0 VSS VSS DMI_TXP2 VSS DMI_TXN0 Y W EXP_TXN15 VSS DMI_TXP0 W V VCC VSS VCC_EXP VSS VSS VCC_EXP VCC_EXP VSS VCC_EXP VCC_EXP VCC_EXP EXP_TXP15 VSS EXP_TXN14 V U VCC VSS VCC_EXP VSS EXP_ RXP12 EXP_ RXN12 VSS VCC_EXP VCC_EXP VCC_EXP VSS EXP_TXN13 VSS EXP_TXP14 U T EXP_TXP13 VSS EXP_TXN12 T R VCC VSS VCC_EXP VSS VCC_EXP VCC_EXP VSS P VSS VSS EXP_ RXP13 EXP_ RXN13 N VSS VSS VCC_EXP VCC_EXP VCC_EXP VCC_EXP VSS VCC_EXP VSS VCC_EXP M RSV VSS RSV VSS VSS VSS EXP_ RXN10 VSS VCC_EXP R EXP_ RXP10 EXP_ RXP14 VSS EXP_TXP12 P EXP_ RXN14 VSS EXP_TXN11 N VSS EXP_TXN10 VSS EXP_TXP11 M L RSV VSS VSS EXP_TXP10 VSS K VSS VSS VSS VSS EXP_RXP8 EXP_RXN8 VSS VSS VSS EXP_TXN9 VSS J DREFCLKP EXP_RXP2 VSS VSS EXP_RXP4 VSS EXP_RXN7 VSS EXP_TXP9 VSS EXP_TXN8 J H DREFCLKN EXP_RXN2 VSS EXP_RXN4 H G VSS VSS EXP_RXP0 VSS VSS VSS EXP_RXP7 VSS EXP_RXN9 VSS EXP_TXP8 G F E SDVO_ CTRLDATA 1 SDVO_ CTRLCLK 1 EXP_ RXP11 EXP_ RXN11 VSS EXP_RXN0 EXP_RXN3 EXP_RXN5 EXP_RXP5 VSS EXP_RXP9 VSS EXP_TXN7 F VSS VSS EXP_RXP3 VSS VSS VSS VSS EXP_TXP7 E D EXP_TXP0 EXP_RXN1 EXP_RXP1 VSS EXP_TXP5 EXP_TXN5 VSS EXP_RXN6 VSS VSS D C VSS EXP_TXN0 VSS EXP_TXP3 EXP_TXN3 VSS VSS EXP_RXP6 VSS NC C B GCLKP VSS EXP_TXN1 VSS EXP_TXN2 VSS EXP_TXN4 VSS EXP_TXN6 VSS NC NC B A EXP_TXP1 EXP_TXP2 EXP_TXP4 EXP_TXP6 VSS A 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 NOTES: 1. This analog display signal ball is reserved on the 82945P/82945PL MCH component. L K
12.2 Ballout Table Ballout and Package Information Table 12-1 lists the Intel ® 82945G/82945GC/82945GZ GMCH and Intel ® 82945P/82945PL MCH ballout in alphabetical order by signal name. Table 12-1. Intel ® 82945G//82945GZ/82945GC/82945P/82945PL (G)MCH Ballout Sorted by Signal Name Intel ® 82945G GMCH Signal Name Intel ® 82945GZ (82945GC) GMCH Signal Name Intel ® 82945P /82945PL MCH Signal Name ALLZTEST ALLZTEST ALLZTEST K18 BLUE BLUE RSV H18 BLUE# BLUE# RSV J18 BSEL0 BSEL0 BSEL0 F21 BSEL1 BSEL1 BSEL1 H21 BSEL2 BSEL2 BSEL2 L20 DDC_CLK DDC_CLK RSV N20 DDC_DATA DDC_DATA RSV N18 DMI_RXN0 DMI_RXN0 DMI_RXN0 Y8 Ball # DMI_RXN1 DMI_RXN1 DMI_RXN1 AA10 DMI_RXN2 DMI_RXN2 DMI_RXN2 AA7 DMI_RXN3 DMI_RXN3 DMI_RXN3 AC8 DMI_RXP0 DMI_RXP0 DMI_RXP0 Y7 DMI_RXP1 DMI_RXP1 DMI_RXP1 AA9 DMI_RXP2 DMI_RXP2 DMI_RXP2 AA6 DMI_RXP3 DMI_RXP3 DMI_RXP3 AC9 DMI_TXN0 DMI_TXN0 DMI_TXN0 Y1 DMI_TXN1 DMI_TXN1 DMI_TXN1 AB1 DMI_TXN2 DMI_TXN2 DMI_TXN2 AA4 DMI_TXN3 DMI_TXN3 DMI_TXN3 AC4 DMI_TXP0 DMI_TXP0 DMI_TXP0 W2 DMI_TXP1 DMI_TXP1 DMI_TXP1 AA2 DMI_TXP2 DMI_TXP2 DMI_TXP2 Y4 DMI_TXP3 DMI_TXP3 DMI_TXP3 AB3 DREFCLKN DREFCLKN DREFCLKN H15 DREFCLKP DREFCLKP DREFCLKP J15 EXP_COMPI RSV (EXP_COMPI) EXP_COMPI AC11 EXP_COMPO RSV (EXP_COMP0) EXP_COMPO AC12 EXP_EN EXP_EN EXP_EN F20 EXP_RXN0 RSV (EXP_RXN0) EXP_RXN0 F12 EXP_RXN1 RSV (EXP_RXN1) EXP_RXN1 D12 275
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Intel ® 945G/945GZ/945GC/ 945P/945
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Contents 1 Introduction ...........
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4.2.11 C0DRC1—Channel A DRAM Cont
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6.1.16 DMICESTS—DMI Correctable E
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9.4.5 SMM Space Decode and Transact
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11.3 DC Characteristics ...........
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Revision History Rev Description Da
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Intel ® 82945G/82945GZ/82945GC/829
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1 Introduction Introduction The Int
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Figure 1-2. Intel ® 945GZ/82945GC
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1.1 Terminology Term Description Ac
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Term Description TOLM Top Of Low Me
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Introduction � Supports four bank
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Introduction 1.4 Graphics (Intel ®
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1.5 Analog and SDVO Displays (Intel
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2 Signal Description Signal Descrip
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2.1 Host Interface Signals Signal D
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Signal Name Type Description HREQ[4
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2.3 DDR2 DRAM Channel B Interface S
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Signal Description 2.6 Analog Displ
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2.8 Direct Media Interface (DMI) Si
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2.10 Power and Ground Name Voltage
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Interface Signal Name I/O System Me
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Interface Signal Name I/O State Dur
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3 Register Description Register Des
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Register Description Note: A physic
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3.3 Configuration Mechanisms Regist
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3.4 Routing Configuration Accesses
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3.4.2.2 DMI Configuration Accesses
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Bit Access & Default 10:8 R/W 000b
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Host Bridge/DRAM Controller Registe
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4.1 Device 0 Configuration Register
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4.1.4 PCISTS—PCI Status (D0:F0) P
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4.1.7 MLT—Master Latency Timer (D
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4.1.12 EPBAR—Egress Port Base Add
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4.1.19 PAM1—Programmable Attribut
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4.1.25 LAC—Legacy Access Control
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4.1.29 ERRSTS—Error Status (D0:F0
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4.1.31 SKPD—Scratchpad Data (D0:F
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4.2.7 C0DCLKDIS—Channel A DRAM Cl
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4.2.9 C0DRT1—Channel A DRAM Timin
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Bit Access & Default 6:4 R/W 000b 3
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4.2.24 PMSTS—Power Management Sta
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4.3.1 EPESD—EP Element Self Descr
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4.3.3 EPLE1A—EP Link Entry 1 Addr
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Host-PCI Express* Bridge Registers
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Address Offset Host-PCI Express* Br
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5.1.3 PCICMD1—PCI Command (D1:F0)
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5.1.4 PCISTS1—PCI Status (D1:F0)
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5.1.7 CL1—Cache Line Size (D1:F0)
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5.1.12 IOBASE1—I/O Base Address (
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5.1.15 MBASE1—Memory Base Address
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5.1.20 INTRLINE1—Interrupt Line (
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Bit Access & Default 2 R/W 0b 1 R/W
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5.1.29 MA—Message Address (D1:F0)
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5.1.33 DCAP—Device Capabilities (
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5.1.35 DSTS—Device Status (D1:F0)
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5.1.37 LCTL—Link Control (D1:F0)
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5.1.39 SLOTCAP—Slot Capabilities
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5.1.41 SLOTSTS—Slot Status (D1:F0
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5.1.43 RSTS—Root Status (D1:F0) P
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5.1.56 ESD—Element Self Descripti
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5.1.61 CESTS—Correctable Error St
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Direct Media Interface (DMI) RCRB 6
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6.1.3 DMIPVCCAP2—DMI Port VC Capa
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6.1.6 DMIVC0RCTL—DMI VC0 Resource
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6.1.9 DMIVC1RCTL—DMI VC1 Resource
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6.1.13 DMILSTS—DMI Link Status MM
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6.1.15 DMIUEMSK—DMI Uncorrectable
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Integrated Graphics Device (D2:F0)
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7.1.4 PCISTS2—PCI Status (D2:F0)
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7.1.7 CLS—Cache Line Size (D2:F0)
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7.1.11 IOBAR—I/O Base Address (D2
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7.1.20 MINGNT—Minimum Grant (D2:F
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8.1.3 PCICMD2—PCI Command (D2:F1)
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8.1.5 RID2—Revision Identificatio
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8.2 Device 2 - PCI I/O Registers In
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9 System Address Map System Address
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Figure 9-1. System Address Ranges 4
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Compatible SMRAM Address Range (A_0
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9.2 Main Memory Address Range (1 MB
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9.3 PCI Memory Address Range (TOLUD
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9.3.6 PCI Express* Graphics Attach
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9.4.1 SMM Space Definition System A
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9.4.5 SMM Space Decode and Transact
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9.4.12 Legacy VGA and I/O Range Dec
Page 223 and 224: 10 Functional Description This chap
Page 225 and 226: Interleaved Mode Functional Descrip
Page 227 and 228: 667 MHz (PC 5300) (82945G/82945GC/8
Page 229 and 230: 10.2.2.2 System Memory Supported Co
Page 231 and 232: Functional Description Table 10-5.
Page 233 and 234: 10.3 PCI Express* (Intel ® 82945G/
Page 235 and 236: Figure 10-2. SDVO Conceptual Block
Page 237 and 238: Figure 10-3. Concurrent SDVO / PCI
Page 239 and 240: 10.5 Integrated Graphics Device (In
Page 241 and 242: 10.5.3 4X Faster Setup Engine Funct
Page 243 and 244: 10.5.4 Texture Engine Functional De
Page 245 and 246: 10.5.4.8 Pixel Shader Functional De
Page 247 and 248: Functional Description to determine
Page 249 and 250: 10.5.6 2D Engine Functional Descrip
Page 251 and 252: 10.5.8.1 Cursor Plane Functional De
Page 253 and 254: Functional Description device is in
Page 255 and 256: 10.6.2 Digital Display Interface Fu
Page 257 and 258: 10.6.2.1.5 Control Bus Functional D
Page 259 and 260: Figure 10-7 illustrates the various
Page 261 and 262: 11 Electrical Characteristics Elect
Page 263 and 264: 11.1.1 Power Characteristics Table
Page 265 and 266: Signal Group Electrical Characteris
Page 267 and 268: 11.3 DC Characteristics Table 11-5.
Page 269 and 270: Symbol Signal Group Electrical Char
Page 271 and 272: Ballout and Package Information 12
Page 273: Ballout and Package Information Fig
Page 277 and 278: Ballout and Package Information EXP
Page 279 and 280: Ballout and Package Information HA2
Page 281 and 282: Ballout and Package Information HD6
Page 283 and 284: Ballout and Package Information RSV
Page 285 and 286: Ballout and Package Information SDM
Page 287 and 288: Ballout and Package Information SDQ
Page 289 and 290: Ballout and Package Information SDQ
Page 291 and 292: Ballout and Package Information VCC
Page 297 and 298: Ballout and Package Information VSS
Page 305 and 306: 12.3 Package § Ballout and Package
Page 307 and 308: Ballout and Package Information Int
Page 309 and 310: 13.2 XOR Test Mode Initialization T
Page 311 and 312: 13.4 XOR Chains Testability Table 1
Page 313 and 314: Table 13-5. XOR Chain 2 Pin Count B
Page 315 and 316: Table 13-8. XOR Chain 5 Pin Count B
Page 317 and 318: Table 13-11. XOR Chain 8 Pin Count
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Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

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