Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

Functional Description
10.7 Power Management
Power management feature List:
258
� ACPI 1.0b support
10.8 Clocking
� ACPI S0, S1D, S3 (both Cold and Chipset Hot), S4, S5, C0, and C1. C2, C3, C4 states and
corresponding Enhanced states- S3hot, C2, C3, and C4 are not used in the (G)MCH.
� Enhanced power management state transitions for increasing time processor spends in low
power states
� Internal Graphics Display Device Control D0, D1, D2, D3
� Graphics Adapter States: D0, D3
� PCI Express Link States: L0, L0s (82945G/82945GC/82945P/82945PL Only)
The (G)MCH has a total of 5 PLLs providing many times that many internal clocks. The PLLs
are:
� Host PLL – This PLL generates the main core clocks in the host clock domain. The Host PLL
can also be used to generate memory and internal graphics core clocks. It uses the Host clock
(HCLKIN) as a reference.
� Memory PLL – This PLL can be used to generate memory and internal graphics core clocks,
when not generated by the Host PLL. The memory PLL is not needed in all configurations,
but exists to provide more flexible frequency combinations without an unreasonable VCO
frequency. It uses the Host clock (HCLKIN) as a reference.
� PCI Express PLL – This PLL generates all PCI Express related clocks, including the Direct
Media Interface that connects to the ICH7. The PCI Express PLL uses the 100 MHz
(GCLKIN) as a reference.
� Display PLL A (82945G/82945GC/82945GZ GMCH Only) – This PLL generates the
internal clocks for Display A. It uses DREFCLK as a reference.
� Display PLL B (82945G/82945GC/82945GZ GMCH Only) – This PLL generates the
internal clocks for Display B. It uses DREFCLK as a reference.