Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...
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Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ... Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

intel
16.08.2012 Views

Functional Description 10.5.8.3 Advanced Deinterlacing and Dynamic Bob and Weave 10.5.9 Pipes Interlaced data that originates from a video camera creates two fields that are temporally offset by 1/60 of a second. There are several schemes to deinterlace the video stream: line replication, vertical filtering, field merging, and vertical temporal filtering. Field merging takes lines from the previous field and inserts them into the current field to construct the frame – this is known as Weaving. This is the best solution for images with little motion; however, showing a frame that consists of the two fields will have serration or feathering of moving edges when there is motion in the scene. Vertical filtering or “Bob” interpolates adjacent lines rather replicating the nearest neighbor. This is the best solution for images with motion; however, it will have reduced spatial resolution in areas that have no motion and introduces jaggies. In absence of any other deinterlacing, these form the baseline and are supported by the GMCH. Scaling Filter and Control The scaling filter has three vertical taps and five horizontal taps. Arbitrary scaling (per pixel granularity) for any video source (YUV422 or YUV420) format is supported. The overlay logic can scale an input image up to 1600X1200 with no major degradation in the filter used as long as the maximum frequency limitation is met. Display resolution and refresh rate combinations where the dot clock is greater than the maximum frequency require the overlay to use pixel replication. The display consists of two pipes. The pipes can operate in a single-wide or “double-wide” mode at 2x graphics core clock though they are effectively limited by the respective display port. The display planes and the cursor plane will provide a “double wide” mode to feed the pipe. 10.5.9.1 Clock Generator Units (DPLL) The clock generator units provide a stable frequency for driving display devices. It operates by converting an input reference frequency into an output frequency. The timing generators take their input from internal DPLL devices that are programmable to generate pixel clocks in the range of 25–400 MHz. Accuracy for VESA timing modes is required to be within ±0.5%. The DPLL can take a reference frequency from the external reference input (DREFCLKN/P) or the TV clock input (SDVO_TVCLKIN+/-). 10.6 Display Interfaces (Intel ® 82945G/82945GC/82945GZ GMCH Only) The GMCH has three display ports; one analog and two digital. Each port can transmit data according to one or more protocols. The digital ports are connected to an external device that converts one protocol to another. Examples of this are TV encoders, external DACs, LVDS transmitters, and TMDS transmitters. Each display port has control signals that may be used to control, configure, and/or determine the capabilities of an external device. The GMCH has one dedicated display port; the analog port. SDVO ports B and C are multiplexed with the PCI Express graphics interface and are not available if an external PCI Express graphics 252

Functional Description device is in use. When a system uses a PCI Express graphics connector, SDVO ports B and C can be used via an ADD2/ADD2+ (Advanced Digital Display 2) card. Ports B and C can also operate in dual-channel mode, where the data bus is connected to both display ports, allowing a single device to take data at twice the pixel rate. � The GMCH’s analog port uses an integrated 400 MHz RAMDAC that can directly drive a standard progressive scan analog monitor up to a resolution of 2048x1536 pixels with 32-bit color at 75 Hz. � The GMCH’s SDVO ports are each capable of driving a 200-MP pixel rate. Each port is capable of driving a digital display up to 1600x1200 @ 60 Hz. When in dual-channel mode, the GMCH can drive a flat panel up to 2048x1536 @ 75 Hz or dCRT/HDTV up to 1920x1080 @ 85 Hz. The GMCH is compliant with DVI Specification 1.0. When combined with a DVI compliant external device and connector, the GMCH has a high speed interface to a digital display (e.g., flat panel or digital CRT). Table 10-7. Display Port Characteristics Signals Analog Digital Port B Digital Port C Interface Protocol RGB DAC DVO 1.0 DVO 1.0 HSYNC Yes Enable/Polarity VSYNC Yes Enable/Polarity BLANK No Yes (1) Yes (1) STALL No Yes Yes Field No Yes Yes Display_Enable No — No Image Aspect Ratio Programmable and typically 1.33:1 or 1.78:1 Pixel Aspect Ratio Square (1) Voltage RGB 0.7 V p-p PCI Express* PCI Express Clock NA Differential Max Rate 400 Mpixel 200/400 Mpixel Format Analog RGB RGB 8:8:8 YUV 4:4:4 Control Bus DDC1/DDC2B DDC2B External Device No TMDS/LVDS Transmitter /TV Encoder Connector VGA/DVI-I DVI/CVBS/S-Video/Component/SCART NOTES: 1. Single signal software selectable between display enable and Blank#. 10.6.1 Analog Display Port Characteristics The analog display port provides a RGB signal output along with a HSYNC and VSYNC signal. There is an associated DDC signal pair that is implemented using GPIO pins dedicated to the analog port. The intended target device is for a CRT based monitor with a VGA connector. Display devices (such as, LCD panels with analog inputs) may work satisfactorily but no functionality has been added to the signals to enhance that capability. 253

Functional Description<br />

device is in use. When a system uses a PCI <strong>Express</strong> graphics connector, SDVO ports B and C can<br />

be used via an ADD2/ADD2+ (Advanced Digital Display 2) card. Ports B and C can also operate<br />

in dual-channel mode, where the data bus is connected to both display ports, allowing a single<br />

device to take data at twice the pixel rate.<br />

� The GMCH’s analog port uses an integrated 400 MHz RAMDAC that can directly drive a<br />

standard progressive scan analog monitor up to a resolution of 2048x1536 pixels with 32-bit<br />

color at 75 Hz.<br />

� The GMCH’s SDVO ports are each capable of driving a 200-MP pixel rate. Each port is<br />

capable of driving a digital display up to 1600x1200 @ 60 Hz. When in dual-channel mode,<br />

the GMCH can drive a flat panel up to 2048x1536 @ 75 Hz or dCRT/HDTV up to<br />

1920x1080 @ 85 Hz.<br />

The GMCH is compliant with DVI Specification 1.0. When combined with a DVI compliant<br />

external device and connector, the GMCH has a high speed interface to a digital display<br />

(e.g., flat panel or digital CRT).<br />

Table 10-7. Display Port Characteristics<br />

Signals<br />

Analog Digital Port B Digital Port C<br />

Interface Protocol RGB DAC DVO 1.0 DVO 1.0<br />

HSYNC Yes Enable/Polarity<br />

VSYNC Yes Enable/Polarity<br />

BLANK No Yes (1) Yes (1)<br />

STALL No Yes Yes<br />

Field No Yes Yes<br />

Display_Enable No — No<br />

Image Aspect Ratio Programmable and typically 1.33:1 or 1.78:1<br />

Pixel Aspect Ratio Square (1)<br />

Voltage RGB 0.7 V p-p PCI <strong>Express</strong>* PCI <strong>Express</strong><br />

Clock NA Differential<br />

Max Rate 400 Mpixel 200/400 Mpixel<br />

Format Analog RGB RGB 8:8:8 YUV 4:4:4<br />

Control Bus DDC1/DDC2B DDC2B<br />

External Device No TMDS/LVDS Transmitter /TV Encoder<br />

Connector VGA/DVI-I DVI/CVBS/S-Video/Component/SCART<br />

NOTES:<br />

1. Single signal software selectable between display enable and Blank#.<br />

10.6.1 Analog Display Port Characteristics<br />

The analog display port provides a RGB signal output along with a HSYNC and VSYNC signal.<br />

There is an associated DDC signal pair that is implemented using GPIO pins dedicated to the<br />

analog port. The intended target device is for a CRT based monitor with a VGA connector.<br />

Display devices (such as, LCD panels with analog inputs) may work satisfactorily but no<br />

functionality has been added to the signals to enhance that capability.<br />

253

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