Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

Functional Description
10.5.8.3 Advanced Deinterlacing and Dynamic Bob and Weave
10.5.9 Pipes
Interlaced data that originates from a video camera creates two fields that are temporally offset by
1/60 of a second. There are several schemes to deinterlace the video stream: line replication,
vertical filtering, field merging, and vertical temporal filtering. Field merging takes lines from the
previous field and inserts them into the current field to construct the frame – this is known as
Weaving. This is the best solution for images with little motion; however, showing a frame that
consists of the two fields will have serration or feathering of moving edges when there is motion
in the scene. Vertical filtering or “Bob” interpolates adjacent lines rather replicating the nearest
neighbor. This is the best solution for images with motion; however, it will have reduced spatial
resolution in areas that have no motion and introduces jaggies. In absence of any other
deinterlacing, these form the baseline and are supported by the GMCH.
Scaling Filter and Control
The scaling filter has three vertical taps and five horizontal taps. Arbitrary scaling (per pixel
granularity) for any video source (YUV422 or YUV420) format is supported.
The overlay logic can scale an input image up to 1600X1200 with no major degradation in the
filter used as long as the maximum frequency limitation is met. Display resolution and refresh rate
combinations where the dot clock is greater than the maximum frequency require the overlay to
use pixel replication.
The display consists of two pipes. The pipes can operate in a single-wide or “double-wide” mode
at 2x graphics core clock though they are effectively limited by the respective display port. The
display planes and the cursor plane will provide a “double wide” mode to feed the pipe.
10.5.9.1 Clock Generator Units (DPLL)
The clock generator units provide a stable frequency for driving display devices. It operates by
converting an input reference frequency into an output frequency. The timing generators take
their input from internal DPLL devices that are programmable to generate pixel clocks in the
range of 25–400 MHz. Accuracy for VESA timing modes is required to be within ±0.5%.
The DPLL can take a reference frequency from the external reference input (DREFCLKN/P) or
the TV clock input (SDVO_TVCLKIN+/-).
10.6 Display Interfaces (Intel ® 82945G/82945GC/82945GZ
GMCH Only)
The GMCH has three display ports; one analog and two digital. Each port can transmit data
according to one or more protocols. The digital ports are connected to an external device that
converts one protocol to another. Examples of this are TV encoders, external DACs, LVDS
transmitters, and TMDS transmitters. Each display port has control signals that may be used to
control, configure, and/or determine the capabilities of an external device.
The GMCH has one dedicated display port; the analog port. SDVO ports B and C are multiplexed
with the PCI Express graphics interface and are not available if an external PCI Express graphics
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