Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

Introduction
� Supports four banks for all DDR2 devices up to 512-Mbit density. Supports eight banks for
1-Gbit DDR2 devices.
� DDR2-667 4-4-4 is Not supported.
� Supports only unbuffered DIMMs.
� Supports opportunistic refresh.
� In dual channel mode the (G)MCH supports 32 simultaneously open pages.
� SPD (Serial Presence Detect) scheme for DIMM detection support.
� Suspend-to-RAM support using CKE.
� Supports configurations defined in the JEDEC DDR2 DIMM specification only.
� Directly supports two channels of non-ECC DDR2 DIMMs.
� Supports Partial Writes to memory using Data Mask (DM) signals.
� Supports a burst length of 8 for single-channel and dual-channel interleaved and asymmetric
operating modes.
� Supports Enhanced Memory Interleave.
1.3.3 Direct Media Interface (DMI)
Direct Media Interface (DMI) is the chip-to-chip connection between the (G)MCH and I/O
Controller Hub 7 (ICH7). This high-speed interface integrates advanced priority-based servicing
allowing for concurrent traffic and true isochronous transfer capabilities. Base functionality is
completely software transparent permitting current and legacy software to operate normally.
To provide for true isochronous transfers and configurable Quality of Service (QoS) transactions,
the ICH7 supports two virtual channels on DMI: VC0 and VC1. These two channels provide a
fixed arbitration scheme where VC1 is always the highest priority. VC0 is the default conduit of
traffic for DMI and is always enabled. VC1 must be specifically enabled and configured at both
ends of the DMI link (i.e., the ICH7 and (G)MCH).
Configuration registers for DMI, virtual channel support, and DMI active state power
management (ASPM) are in the RCRB space in the (G)MCH Register Description.
� A chip-to-chip connection interface to the ICH7
� 2 GB/s point-to-point DMI to ICH7 (1 GB/s each direction)
� 100 MHz reference clock (shared with PCI Express graphics attach)
� 32-bit downstream addressing
� APIC and MSI interrupt messaging support. Will send Intel-defined “End Of Interrupt”
broadcast message when initiated by the processor.
� Message Signaled Interrupt (MSI) messages
� SMI, SCI, and SERR error indication
� Legacy support for ISA regime protocol (PHOLD/PHOLDA) required for parallel port
DMA, floppy drive, and LPC bus masters
Intel ® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet 25