Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

Introduction
1.3.1 Host Interface
The (G)MCH is optimized for the Intel ® Atom TM 200 Series, Intel ® Atom TM 300 Series based on
45nm process technology in a FCBGA 437 pins socket, Intel ® Core TM 2 Duo, Intel ® Celeron 400
series, Intel ® Pentium 4 processor in the 90 nm process in the LGA775 Land Grid Array package
and Intel ® Pentium D processor in a LGA775 socket; Only the 82945GC (G)MCH are designed
for use with Intel ® Atom TM 200 Series and Intel ® Atom TM 300 Series. The (G)MCH supports FSB
frequencies using a scalable FSB Vcc_CPU. FSB frequencies supported are 133 MHz
(533 MT/s), 200 MHz (800 MT/s), and 266 MHz (1066 MT/s); only the 82945G/82945P
(G)MCH support 266 MHz (1066 MT/s).
The (G)MCH supports the Pentium 4 processor subset of the Extended Mode Scaleable Bus
Protocol. The primary enhancements over the Compatible Mode P6 bus protocol are source
synchronous double-pumped (2x) address and source synchronous quad-pumped (4x) data. Other
(G)MCH supported features of the host interface include: Hyper-Threading Technology (HT
Technology), Pentium 4 processor FSB interrupt delivery, FSB Dynamic Bus Inversion (DBI),
12-deep in-order queue, and a 1-deep defer queue.
The (G)MCH supports 32-bit host addressing, decoding up to 4 GB (2 GB for the
82945PL/82945GC/82945GZ) of the processor’s usable memory address space. Host-initiated I/O
cycles are decoded to PCI Express, DMI, or the (G)MCH configuration space. Host-initiated
memory cycles are decoded to PCI Express, DMI or main memory. PCI Express device accesses
to non-cacheable system memory are not snooped on the host bus. Memory accesses initiated
from PCI Express using PCI semantics and from DMI to system SDRAM will be snooped on the
host bus.
1.3.2 System Memory Interface
The (G)MCH integrates a system memory DDR2 controller with two, 64-bit wide interfaces.
Only Double Data Rate (DDR2) memory is supported; consequently, the buffers support only
SSTL_1.8 V signal interfaces. The memory controller interface is fully configurable through a set
of control registers. Features of the (G)MCH memory controller include:
� Maximum memory size:
� 4 GB for 82945G GMCH and 82945P MCH
� 2 GB for 82945GZ/82945GC GMCH and 82945PL MCH
� Directly supports one or two channels of memory (each channel consisting of 64 data lines)
� The memory channels are asymmetric: "Stacked" channels are assigned addresses
serially. Channel B addresses are assigned after all Channel A addresses.
� The memory channels are interleaved: Addresses are ping-ponged between the channels
after each cache line (64-B boundary).
� Supports DDR2 400, DDR2 533, and DDR2 667. DDR2 667 is supported on
82945G/82945GC/82945P Only.
� Available bandwidth up to 5.3 GB/s (DDR2 667) for single-channel mode or dual-channel
asymmetric mode and 10.7 GB/s (DDR2 667) in dual-channel Interleaved mode.
� Supports DDR2 memory DIMM frequencies of 400 MHz, 533 MHz, and
667 MHz (82945G/82945GC/82945P Only). The speed used in all channels is the speed of
the slowest DIMM in the system.
� Supports 256-Mb, 512-Mb, and 1-Gb DDR2 technologies for x8 and x16 devices.
24 Intel ® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet