Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

10.3 PCI Express* (Intel ® 82945G/82945GC/
82945P/82945PL (G)MCH Only)
Functional Description
Refer to Section 1.3.4 for list of PCI Express features, and the PCI Express specification for
further details. Refer to Section 10.4 for additional information on the features/capabilities of the
multiplexed PCI Express interface and SDVO ports.
The (G)MCH is part of a PCI Express root complex. This means it connects a host
processor/memory subsystem to a PCI Express hierarchy. The control registers for this
functionality are located in device 1 configuration space and two Root Complex Register Blocks
(RCRBs). The DMI RCRB contains registers for control of the ICH7 attach ports.
The PCI Express architecture is specified in layers. Compatibility with the PCI addressing model
(a load-store architecture with a flat address space) is maintained to ensure that all existing
applications and drivers operate unchanged. The PCI Express configuration uses standard
mechanisms as defined in the PCI Plug-and-Play specification. The initial speed of 1.25 GHz
(250 MHz internally) results in 2.5 Gb/s/direction that provides a 250 MB/s communications
channel in each direction (500 MB/s total) that is close to twice the data rate of classic PCI per
lane.
10.3.1 Transaction Layer
The upper layer of the PCI Express architecture is the Transaction Layer. The Transaction Layer’s
primary responsibility is the assembly and disassembly of Transaction Layer Packets (TLPs).
TLPs are used to communicate transactions, such as read and write, as well as certain types of
events. The Transaction Layer also manages flow control of TLPs.
10.3.2 Data Link Layer
The middle layer in the PCI Express stack, the Data Link Layer, serves as an intermediate stage
between the Transaction Layer and the Physical Layer. Responsibilities of Data Link Layer
include link management, error detection, and error correction.
10.3.3 Physical Layer
The Physical Layer includes all circuitry for interface operation, including driver and input
buffers, parallel-to-serial and serial-to-parallel conversion, PLL(s), and impedance matching
circuitry.
233