Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

Functional Description
10.2.3 DRAM Clock Generation
The (G)MCH generates three differential clock pairs for every supported DIMM. There are a total
of 6 clock pairs driven directly by the (G)MCH to 2 DIMMs per channel.
10.2.4 Suspend to RAM and Resume
When entering the Suspend to RAM (STR) state, the SDRAM controller will flush pending cycles
and then enter all SDRAM rows into self refresh. In STR, the CKE signals remain Low so the
SDRAM devices will perform self-refresh.
10.2.5 DDR2 On Die Termination
On die termination (ODT) is a feature that allows a DRAM to turn on/off internal termination
resistance for each SDQ_x, SDM_x, SDQS_x, and SDQS_x# signal for x8 and x16
configurations via the SODT_x control signals. The SODT_x feature is designed to improve
signal integrity of the memory channel by allowing the termination resistance for the SDQ_x,
SDM_x, SDQS_x, and SDQS_x# signals to be located inside the DRAM devices themselves
instead of on the motherboard. The (G)MCH drives out the required SODT_x signals, based on
memory configuration and which rank is being written to or read from, to the DRAM devices on a
targeted DIMM rank to enable or disable their termination resistance.
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