Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

Functional Description
10.2.1 System Memory Configuration Registers Overview
The configuration registers located in the PCI configuration space of the (G)MCH control the
system memory operation. Following is a brief description of configuration registers.
� DRAM Rank Boundary (CxDRBy): The x represents a channel, either A or B. The y
represents a rank, 0 through 3. DRB registers define the upper addresses for a rank of DRAM
devices in a channel. When the (G)MCH is configured in asymmetric mode, each register
represents a single rank. When the (G)MCH is configured in a dual interleaved mode, each
register represents a pair of corresponding ranks in opposing channels. There are 4 DRB
registers for each channel.
� DRAM Rank Architecture (CxDRAy): The x represents a channel, either A or B. The y
represents a rank, 0 through 3. DRA registers specify the architecture features of each rank of
devices in a channel. The only architecture feature specified is page size. When the (G)MCH
is configured in asymmetric mode, each DRA represents a single rank in a single channel.
When (G)MCH is configured in a dual-channel interleaved mode, each DRA represents a
pair of corresponding ranks in opposing channels. There are 4 DRA registers per channel.
Each requires only 3 bits, so there are two DRAs packed into a byte.
� Clock Configuration (CLKCFG): CLKCFG specifies DRAM frequency. The same clock
frequency will be driven to all DIMMs.
� DRAM Timing (CxDRT1): The x represents a channel, A or B represented by 0 and 1
respectively. The DRT Register defines the timing parameters for all devices in a channel.
BIOS programs this register with “least common denominator” values after reading the SPD
registers of each DIMM in the channel.
� DRAM Control (CxDRC0): The x represents a channel, A or B represented by 0 and 1
respectively. DRAM refresh mode, rate, and other controls are selected here.
10.2.2 DRAM Technologies and Organization
"Single sided" below is a logical term referring to the number of chip selects attached to the
DIMM. A real DIMM may put the components on both sides of the substrate, but be logically
indistinguishable from single-sided DIMM if all components on the DIMM are attached to the
same chip select signal.
� x8 means that each component has 8 data lines.
� x16 means that each component has 16 data lines
All standard 256-Mb, 512-Mb, and 1-Gb technologies and addressing are supported for x16 and
x8 devices.
For DDR2:
400 MHz (PC2 3200)
Non-ECC
Version A = Single sided x8
Version B = Double sided x8
Version C = Single sided x16
533 MHz (PC 4300)
Non-ECC
Version A = Single sided x8
Version B = Double sided x8
Version C = Single sided x16
226 Intel ® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet