Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

10 Functional Description
This chapter describes the (G)MCH interfaces and major functional units.
10.1 Host Interface
Functional Description
The (G)MCH supports the Pentium ® 4 processor subset of the Enhanced Mode Scaleable Bus.
The cache line size is 64 bytes. Source synchronous transfer is used for the address and data
signals. The address signals are double pumped and a new address can be generated every other
bus clock. At 200/267 MHz bus clock, the address signals run at 400/533MT/s. The data is quad
pumped and an entire 64 B cache line can be transferred in two bus clocks. At 200/267 MHz bus
clock, the data signals run at 800/1066MT/s for a maximum bandwidth of 10.7 GB/s.
10.1.1 FSB IOQ Depth
The Scalable bus supports up to 12 simultaneous outstanding transactions.
10.1.2 FSB OOQ Depth
The (G)MCH supports only one outstanding deferred transaction on the FSB.
10.1.3 FSB GTL+ Termination
The (G)MCH integrates GTL+ termination resistors on die. Also, approximately 2.8 pf (fast) –
3.3 pf (slow) per pad of on die capacitance will be implemented to provide better FSB electrical
performance.
10.1.4 FSB Dynamic Bus Inversion
The (G)MCH supports Dynamic Bus Inversion (DBI) when driving and when receiving data from
the processor. DBI limits the number of data signals that are driven to a low voltage on each quad
pumped data phase. This decreases the worst-case power consumption of the (G)MCH.
HDINV[3:0]# indicate if the corresponding 16 bits of data are inverted on the bus for each quad
pumped data phase:
HDINV[3:0]# Data Bits
HDINV0# HD15:0#
HDINV1# HD31:16#
HDINV2# HD47:32#
HDINV3# HD63:48#
Intel ® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet 223