Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

System Address Map
9.4.9 I/O Address Space
The (G)MCH does not support the existence of any other I/O devices beside itself on the
processor bus. The (G)MCH generates either DMI or PCI Express bus cycles for all processor I/O
accesses that it does not claim. Within the host bridge, the (G)MCH contains two internal
registers in the processor I/O space: Configuration Address (CONFIG_ADDRESS) register and
the Configuration Data (CONFIG_DATA) register. These locations are used to implement a
configuration space access mechanism.
The processor allows 64 K+3 bytes to be addressed within the I/O space. The (G)MCH
propagates the processor I/O address without any translation on to the destination bus and,
therefore, provides addressability for 64 K+3 byte locations. Note that the upper 3 locations can
be accessed only during I/O address wrap-around when the processor bus HA16# address signal
is asserted. HA16# is asserted on the processor bus whenever an I/O access is made to 4 bytes
from address 0FFFDh, 0FFFEh, or 0FFFFh. HA16# is also asserted when an I/O access is made
to 2 bytes from address 0FFFFh.
A set of I/O accesses (other than ones used for configuration space access) are consumed by the
internal graphics device if it is enabled. The mechanisms for internal graphics I/O decode and the
associated control are explained later.
The I/O accesses (other than ones used for configuration space access) are forwarded normally to
the DMI bus unless they fall within the PCI Express I/O address range as defined by the
mechanisms explained below. I/O writes are not posted. Memory writes to ICH7 or PCI Express
are posted. The PCICMD1 register can disable the routing of I/O cycles to PCI Express.
The (G)MCH responds to I/O cycles initiated on PCI Express or DMI with a UR status. Upstream
I/O cycles and configuration cycles should never occur. If one does occur, the request will route
as a read to memory address 0h so a completion is naturally generated (whether the original
request was a read or write). The transaction will complete with a UR completion status.
For Pentium 4 processors, I/O reads that lie within 8-byte boundaries but cross 4-byte boundaries
are issued from the processor as 1 transaction. The (G)MCH splits this into 2 separate
transactions. I/O writes that lie within 8-byte boundaries but cross 4-byte boundaries are assumed
to be split into 2 transactions by the processor.
9.4.10 PCI Express* I/O Address Mapping
The (G)MCH can be programmed to direct non-memory (I/O) accesses to the PCI Express bus
interface when processor-initiated I/O cycle addresses are within the PCI Express I/O address
range. This range is controlled via the I/O Base Address (IOBASE) and I/O Limit Address
(IOLIMIT) registers in (G)MCH Device 1 configuration space.
9.4.11 (G)MCH Decode Rules and Cross-Bridge Address Mapping
The following are (G)MCH decode rules and cross-bridge address mapping used in this chipset:
� VGAA = 000A_0000 – 000A_FFFF
� MDA = 000B_0000 – 000B_7FFF
� VGAB = 000B_8000 – 000B_FFFF
� MAINMEM = 0100_0000 to TOLUD
220 Intel ® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet