Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

9.4.1 SMM Space Definition
System Address Map
SMM space is defined by its addressed SMM space and its DRAM SMM space. The addressed
SMM space is defined as the range of bus addresses used by the processor to access SMM space.
DRAM SMM space is defined as the range of physical DRAM memory locations containing the
SMM code. SMM space can be accessed at one of three transaction address ranges: Compatible,
High, and TSEG. The Compatible and TSEG SMM space is not remapped; therefore, the
addressed and DRAM SMM space is the same address range. Since the High SMM space is
remapped, the addressed and DRAM SMM space are different address ranges. Note that the High
DRAM space is the same as the Compatible Transaction Address space. The following table
describes three unique address ranges:
� Compatible Transaction Address
� High Transaction Address
� TSEG Transaction Address
SMM Space Enabled Transaction Address Space DRAM Space (DRAM)
Compatible (C) 000A_0000h to 000B_FFFFh 000A_0000h to 000B_FFFFh
High (H) FEDA_0000h to FEDB_FFFFh 000A_0000h to 000B_FFFFh
TSEG (T) (TOLUD-STOLEN-TSEG) to
TOLUD-STOLEN
9.4.2 SMM Space Restrictions
(TOLUD-STOLEN-TSEG) to
TOLUD-STOLEN
If any of the following conditions are not met, the results of SMM accesses are unpredictable and
may cause the system to hang:
� The Compatible SMM space must not be set-up as cacheable.
� High or TSEG SMM transaction address space must not overlap address space assigned to
system DRAM, or to any PCI devices (including DMI, PCI Express, and graphics devices).
This is a BIOS responsibility.
� Both D_OPEN and D_CLOSE must not be set to 1 at the same time.
� When TSEG SMM space is enabled, the TSEG space must not be reported to the operating
system as available DRAM. This is a BIOS responsibility.
� Any address translated through the GMADR TLB must not target DRAM from A_0000–
F_FFFFh.
Intel ® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet 217