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Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

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System Address Map<br />

9.3.8 Graphics Memory Address Ranges (Intel ®<br />

82<strong>945G</strong>/82<strong>945G</strong>C/82<strong>945G</strong>Z GMCH Only)<br />

The GMCH can be programmed to direct memory accesses to IGD when addresses are within any<br />

of three ranges specified via registers in the GMCH’s Device 2 configuration space.<br />

� The Memory Map Base register (MMADR) is used to access graphics control registers.<br />

� The Graphics Memory Aperture Base register (GMADR) is used to access graphics memory<br />

allocated via the graphics translation table.<br />

� The Graphics Translation Table Base register (GTTADR) is used to access the translation<br />

table.<br />

Normally, these ranges will reside above the Top-of-Main-DRAM and below High BIOS and<br />

APIC address ranges. They normally reside above the top of memory (TOLUD) so they do not<br />

steal any physical DRAM memory space.<br />

GMADR is a prefetchable range to apply USWC attribute (from the processor point of view) to<br />

that range. The USWC attribute is used by the processor for write combining.<br />

9.4 System Management Mode (SMM)<br />

System Management Mode uses main memory for System Management RAM (SMM RAM). The<br />

(G)MCH supports Compatible SMRAM (C_SMRAM), High Segment (HSEG), and Top of<br />

Memory Segment (TSEG). System Management RAM space provides a memory area that is<br />

available for the SMI handlers and code and data storage. This memory resource is normally<br />

hidden from the system OS so that the processor has immediate access to this memory space upon<br />

entry to SMM. The (G)MCH provides three SMRAM options:<br />

� Below 1-MB option that supports compatible SMI handlers.<br />

� Above 1-MB option that allows new SMI handlers to execute with write-back cacheable<br />

SMRAM.<br />

� Optional TSEG area of 1 MB, 2 MB, or 8 MB in size. The TSEG area lies below IGD stolen<br />

memory.<br />

The above 1-MB solutions require changes to compatible SMRAM handlers’ code to properly<br />

execute above 1 MB.<br />

Note: DMI and PCI <strong>Express</strong> masters are not allowed to access the SMM space.<br />

216 Intel ® 82<strong>945G</strong>/82<strong>945G</strong>Z/82<strong>945G</strong>C GMCH and 82<strong>945P</strong>/82<strong>945P</strong>L MCH Datasheet

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