Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

9.3.6 PCI Express* Graphics Attach (Intel ®
82945G/82945GC/82945P/82945PL GMCH Only)
System Address Map
The (G)MCH can be programmed to direct memory accesses to the PCI Express interface when
addresses are within either of two ranges specified via registers in the (G)MCH’s Device 1
configuration space.
� The first range is controlled via the Memory Base (MBASE) register and Memory Limit
(MLIMIT) register.
� The second range is controlled via the Prefetchable Memory Base (PMBASE) register and
Prefetchable Memory Limit (PMLIMIT) register.
The (G)MCH positively decodes memory accesses to PCI Express memory address space as
defined by the following inequalities:
Memory_Base_Address � Address � Memory_Limit_Address
Prefetchable_Memory_Base_Address � Address � Prefetchable_Memory_Limit_Address
It is essential to support a separate prefetchable range to apply the USWC attribute (from the
processor point of view) to that range. The USWC attribute is used by the processor for write
combining.
Note: The (G)MCH Device 1 memory range registers described above are used to allocate memory
address space for any PCI Express devices on PCI Express that require such a window.
The PCICMD1 register can override the routing of memory accesses to PCI Express. In other
words, the memory access enable bit must be set in the device 1 PCICMD1 register to enable the
memory base/limit and prefetchable base/limit windows.
9.3.7 AGP DRAM Graphics Aperture
Unlike AGP4x, PCI Express has no concept of aperture for PCI Express devices. As a result,
there is no need to translate addresses from PCI Express. Therefore, the (G)MCH has no
APBASE and APSIZE registers.
Intel ® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet 215