Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

System Address Map
9.2.1 ISA Hole (15 MB–16 MB)
9.2.2 TSEG
A hole can be created at 15 MB–16 MB as controlled by the fixed hole enable bit in the LAC
register (Device 0, offset 97h). Accesses within this hole are forwarded to the DMI. The range of
physical main memory disabled by opening the hole is not remapped to the top of the memory;
that physical main memory space is not accessible. This 15 MB–16 MB hole is an optionally
enabled ISA hole.
Video accelerators originally used this hole. It is also used by validation and customer SV teams
for test cards. That is why it is being supported. There is no inherent BIOS request for the
15–16-MB window.
TSEG is optionally 1 MB, 2 MB, or 8 MB in size. TSEG is below IGD stolen memory, which is
at the top of physical memory. SMM-mode processor accesses to enabled TSEG access the
physical DRAM at the same address. Non- processor originated accesses are not allowed to SMM
space. PCI Express, DMI, and Internal Graphics originated cycles to enabled SMM space are
handled as invalid cycle type with reads and writes to location 0 and byte enables turned off for
writes. When the extended SMRAM space is enabled, processor accesses to the TSEG range
without SMM attribute or without WB attribute are also forwarded to memory as invalid accesses.
Non-SMM-mode Write Back cycles that target TSEG space are completed to DRAM for cache
coherency. When SMM is enabled, the maximum amount of memory available to the system is
equal to the amount of physical DRAM minus the value in the TSEG register that is fixed at 1
MB, 2 MB, or 8 MB.
9.2.3 Pre-allocated Memory
Voids of physical addresses that are not accessible as general system memory and reside within
system memory address range (< TOLUD) are created for SMM-mode and legacy VGA graphics
compatibility. It is the responsibility of BIOS to properly initialize these regions. Table 9-4
details the location and attributes of the regions. How to enable and disable these ranges are
described in the (G)MCH Control Register Device 0 (GCC).
Table 9-4. Pre-Allocated Memory Example for 64-MB DRAM, 1-MB VGA and 1-MB TSEG
Memory Segments Attributes Comments
0000_0000h – 03DF_FFFFh R/W Available system memory 62 MB
03E0_0000h – 03EF_FFFFh SMM mode only -
processor reads
TSEG address range and pre-allocated
memory
03F0_0000h – 03FF_FFFFh R/W Pre-allocated graphics VGA memory.
1 MB (or 4/8/16/32/64 MB) when IGD is
enabled.
212 Intel ® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet