Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

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System Address Map � DMIBAR – This window is used to access registers associated with the (G)MCH/ICH7 (DMI) register memory range. (4-KB window) � IFPBAR – Any write to this window will trigger a flush of the (G)MCH’s Global Write Buffer to let software include coherency between writes from an isochronous agent and writes from the processor (4-KB window). � GGC – GMCH graphics control register (82945G/82945GC/82945GZ GMCH only). This register is used to select the amount of main memory that is pre-allocated to support the internal graphics device in VGA (non-linear) and Native (linear) modes (0–64-MB options). � Device 1, Function 0 � MBASE1/MLIMIT1 – PCI Express port non-prefetchable memory access window. � PMBASE1/PMLIMIT1 – PCI Express port prefetchable memory access window. � IOBASE1/IOLIMIT1 – PCI Express port I/O access window. � Device 2, Function 0 (82945G/82945GC/82945GZ GMCH only) � MMADR – IGD registers and internal graphics instruction port (512-KB window) � IOBAR – I/O access window for internal graphics. Through this window address/data register pair, using I/O semantics, the IGD and internal graphics instruction port registers can be accessed. Note that this allows accessing the same registers as MMADR. In addition, the IOBAR can be used to issue writes to the GTTADR table. � GMADR – Internal graphics translation window (256-MB or 512-MB window) � GTTADR – Internal graphics translation table location (256-KB or 512-KB window). � Device 2, Function 1 (82945G/82945GC/82945GZ GMCH only) � MMADR – Function 1 IGD registers and internal graphics instruction port (512-KB window) The rules for the above programmable ranges are: � ALL of these ranges Must be unique and Non-Overlapping. It is the BIOS or system designer’s responsibility to limit memory population so that adequate PCI, PCI Express , High BIOS, PCI Express memory-mapped space, and APIC memory space can be allocated. � In the case of overlapping ranges with memory, the memory decode will be given priority. � There are No Hardware Interlocks to prevent problems in the case of overlapping ranges. � Accesses to overlapped ranges may produce indeterminate results. � The only peer-to-peer cycles allowed below the top of memory (TOLUD register) are DMI to PCI Express VGA range writes. Note that peer-to-peer cycles to the internal graphics VGA range are not supported. Figure 9-1 shows a simplified form of the the system memory address map. 206 Intel ® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
Figure 9-1. System Address Ranges 4 GB 1 TOLUD 1 MB 0 PCI Memory Address Range (Subtractively decoded to DMI) Main Memory Address Range Legacy Address Range Device 0 Bars (EPBAR, MCHBAR, PCIEXBAR, DMIBAR) Device 0 GGC (Graphics Stolen Memory) Device 1 Bars (MBASE1/ MLIMIT1, PMBASE1/ PMLIMIT1) Device 2 Bars (MMADR, GMADR, GTTADR) Independently Programmable Non-Overlapping Windows Notes: 1. The 4 GB maximum is for the 82945G/82945P only. The maximum addressable space for the 82945GZ/82945PL is 2 GB. 9.1 Legacy Address Range This area is divided into the following address regions: � 0 – 640 KB – DOS Area � 640 – 768 KB – Legacy Video Buffer Area � 768 – 896 KB in 16-KB sections (total of 8 sections) – Expansion Area System Address Map MemMap_SysAdr_Ranges � 896 – 960 KB in 16-KB sections (total of 4 sections) – Extended System BIOS Area � 960-KB – 1-MB Memory – System BIOS Area Intel ® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet 207
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Intel ® 945G/945GZ/945GC/ 945P/945
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Contents 1 Introduction ...........
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4.2.11 C0DRC1—Channel A DRAM Cont
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6.1.16 DMICESTS—DMI Correctable E
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9.4.5 SMM Space Decode and Transact
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11.3 DC Characteristics ...........
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Revision History Rev Description Da
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Intel ® 82945G/82945GZ/82945GC/829
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1 Introduction Introduction The Int
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Figure 1-2. Intel ® 945GZ/82945GC
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1.1 Terminology Term Description Ac
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Term Description TOLM Top Of Low Me
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Introduction � Supports four bank
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Introduction 1.4 Graphics (Intel ®
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1.5 Analog and SDVO Displays (Intel
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2 Signal Description Signal Descrip
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2.1 Host Interface Signals Signal D
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Signal Name Type Description HREQ[4
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2.3 DDR2 DRAM Channel B Interface S
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Signal Description 2.6 Analog Displ
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2.8 Direct Media Interface (DMI) Si
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2.10 Power and Ground Name Voltage
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Interface Signal Name I/O System Me
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Interface Signal Name I/O State Dur
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3 Register Description Register Des
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Register Description Note: A physic
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3.3 Configuration Mechanisms Regist
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3.4 Routing Configuration Accesses
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3.4.2.2 DMI Configuration Accesses
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Bit Access & Default 10:8 R/W 000b
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Host Bridge/DRAM Controller Registe
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4.1 Device 0 Configuration Register
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4.1.4 PCISTS—PCI Status (D0:F0) P
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4.1.7 MLT—Master Latency Timer (D
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4.1.12 EPBAR—Egress Port Base Add
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4.1.19 PAM1—Programmable Attribut
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4.1.25 LAC—Legacy Access Control
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4.1.29 ERRSTS—Error Status (D0:F0
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4.1.31 SKPD—Scratchpad Data (D0:F
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4.2.7 C0DCLKDIS—Channel A DRAM Cl
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4.2.9 C0DRT1—Channel A DRAM Timin
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Bit Access & Default 6:4 R/W 000b 3
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4.2.24 PMSTS—Power Management Sta
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4.3.1 EPESD—EP Element Self Descr
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4.3.3 EPLE1A—EP Link Entry 1 Addr
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Host-PCI Express* Bridge Registers
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Address Offset Host-PCI Express* Br
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5.1.3 PCICMD1—PCI Command (D1:F0)
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5.1.4 PCISTS1—PCI Status (D1:F0)
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5.1.7 CL1—Cache Line Size (D1:F0)
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5.1.12 IOBASE1—I/O Base Address (
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5.1.15 MBASE1—Memory Base Address
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5.1.20 INTRLINE1—Interrupt Line (
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Bit Access & Default 2 R/W 0b 1 R/W
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5.1.29 MA—Message Address (D1:F0)
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5.1.33 DCAP—Device Capabilities (
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5.1.35 DSTS—Device Status (D1:F0)
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5.1.37 LCTL—Link Control (D1:F0)
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5.1.39 SLOTCAP—Slot Capabilities
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5.1.41 SLOTSTS—Slot Status (D1:F0
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5.1.43 RSTS—Root Status (D1:F0) P
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5.1.56 ESD—Element Self Descripti
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Page 157 and 158: 5.1.61 CESTS—Correctable Error St
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Page 161 and 162: Direct Media Interface (DMI) RCRB 6
Page 163 and 164: 6.1.3 DMIPVCCAP2—DMI Port VC Capa
Page 165 and 166: 6.1.6 DMIVC0RCTL—DMI VC0 Resource
Page 167 and 168: 6.1.9 DMIVC1RCTL—DMI VC1 Resource
Page 169 and 170: 6.1.13 DMILSTS—DMI Link Status MM
Page 171 and 172: 6.1.15 DMIUEMSK—DMI Uncorrectable
Page 173 and 174: Integrated Graphics Device (D2:F0)
Page 177 and 178: 7.1.4 PCISTS2—PCI Status (D2:F0)
Page 179 and 180: 7.1.7 CLS—Cache Line Size (D2:F0)
Page 181 and 182: 7.1.11 IOBAR—I/O Base Address (D2
Page 185 and 186: 7.1.20 MINGNT—Minimum Grant (D2:F
Page 193 and 194: 8.1.3 PCICMD2—PCI Command (D2:F1)
Page 195 and 196: 8.1.5 RID2—Revision Identificatio
Page 203 and 204: 8.2 Device 2 - PCI I/O Registers In
Page 205: 9 System Address Map System Address
Page 209 and 210: Compatible SMRAM Address Range (A_0
Page 211 and 212: 9.2 Main Memory Address Range (1 MB
Page 213 and 214: 9.3 PCI Memory Address Range (TOLUD
Page 215 and 216: 9.3.6 PCI Express* Graphics Attach
Page 217 and 218: 9.4.1 SMM Space Definition System A
Page 219 and 220: 9.4.5 SMM Space Decode and Transact
Page 221 and 222: 9.4.12 Legacy VGA and I/O Range Dec
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Page 225 and 226: Interleaved Mode Functional Descrip
Page 227 and 228: 667 MHz (PC 5300) (82945G/82945GC/8
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Page 231 and 232: Functional Description Table 10-5.
Page 233 and 234: 10.3 PCI Express* (Intel ® 82945G/
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10.6.2.1.5 Control Bus Functional D
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Figure 10-7 illustrates the various
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11 Electrical Characteristics Elect
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11.1.1 Power Characteristics Table
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Signal Group Electrical Characteris
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11.3 DC Characteristics Table 11-5.
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Symbol Signal Group Electrical Char
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Ballout and Package Information 12
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Ballout and Package Information Fig
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12.2 Ballout Table Ballout and Pack
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Ballout and Package Information EXP
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Ballout and Package Information HA2
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Ballout and Package Information HD6
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Ballout and Package Information RSV
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Ballout and Package Information SDM
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Ballout and Package Information SDQ
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Ballout and Package Information SDQ
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Ballout and Package Information VCC
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Ballout and Package Information VSS
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12.3 Package § Ballout and Package
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Ballout and Package Information Int
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13.2 XOR Test Mode Initialization T
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13.4 XOR Chains Testability Table 1
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Table 13-5. XOR Chain 2 Pin Count B
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Table 13-8. XOR Chain 5 Pin Count B
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Table 13-11. XOR Chain 8 Pin Count
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Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

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