Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

8.2 Device 2 – PCI I/O Registers
Integrated Graphics Device (D2:F1) Registers (Intel® 82945G/82945GC/82945GZ GMCH Only)
The following are not PCI configuration registers; they are I/O registers.
8.2.1 MMIO Index—MMIO Address Register
I/O Address: IOBAR + 0h
Default: 00000000h
Access: R/W
Size: 32 bits
A 32 bit I/O write to this port loads the offset of the MMIO register that needs to be accessed. An
I/O read returns the current value of this register. An 8/16-bit I/O write to this register is
completed by the GMCH but does not update this register. This mechanism is used to access
internal graphics MMIO registers; however, it must not be used to access VGA I/O registers that
are mapped through the MMIO space. VGA registers must be accessed directly through the
dedicated VGA IO ports.
Bit Access &
Default
31:2 R/W
00000000h
1:0 Reserved
8.2.2 MMIO Data—MMIO Data Register
I/O Address: IOBAR + 4h
Default: 00000000h
Access: R/W
Size: 32 bits
Description
Register Offset: This field selects any one of the DWord registers within the
MMIO register space of Device 2.
A 32 bit I/O write to this port is re-directed to the MMIO register pointed to by the MMIO-index
register. A 32 bit I/O read to this port is re-directed to the MMIO register pointed to by the
MMIO-index register. 8 or 16 bit I/O writes are completed by the GMCH and may have unintended
side effects; hence, must not be used to access the data port. 8 or 16 bit I/O reads are
completed normally.
Bit Access &
Default
31:0 R/W
00000000h
MMIO Data Window
Description
Intel ® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet 203
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