Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

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Integrated Graphics Device (D2:F1) Registers (Intel® 82945G/82945GC/82945GZ GMCH Only) 8.1.26 ASLS—ASL Storage (D2:F1) PCI Device: 2 Address Offset: FCh Default Value: 00000000h Access: R/W Size: 32 bits This software scratch register is read/write accessible. The exact bit register usage must be worked out in common between system BIOS and driver software, but storage for switching/indicating up to 6 devices is possible with this amount. For each device, the ASL control method requires two bits for _DOD (BIOS detectable yes or no, VGA/NonVGA), one bit for _DGS (enable/disable requested), and two bits for _DCS (enabled now/disabled now, connected or not). Bit Access & Default 31:0 R/W 00000000h Description R/W according to a software controlled usage to support device switching. 202 Intel ® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
8.2 Device 2 – PCI I/O Registers Integrated Graphics Device (D2:F1) Registers (Intel® 82945G/82945GC/82945GZ GMCH Only) The following are not PCI configuration registers; they are I/O registers. 8.2.1 MMIO Index—MMIO Address Register I/O Address: IOBAR + 0h Default: 00000000h Access: R/W Size: 32 bits A 32 bit I/O write to this port loads the offset of the MMIO register that needs to be accessed. An I/O read returns the current value of this register. An 8/16-bit I/O write to this register is completed by the GMCH but does not update this register. This mechanism is used to access internal graphics MMIO registers; however, it must not be used to access VGA I/O registers that are mapped through the MMIO space. VGA registers must be accessed directly through the dedicated VGA IO ports. Bit Access & Default 31:2 R/W 00000000h 1:0 Reserved 8.2.2 MMIO Data—MMIO Data Register I/O Address: IOBAR + 4h Default: 00000000h Access: R/W Size: 32 bits Description Register Offset: This field selects any one of the DWord registers within the MMIO register space of Device 2. A 32 bit I/O write to this port is re-directed to the MMIO register pointed to by the MMIO-index register. A 32 bit I/O read to this port is re-directed to the MMIO register pointed to by the MMIO-index register. 8 or 16 bit I/O writes are completed by the GMCH and may have unintended side effects; hence, must not be used to access the data port. 8 or 16 bit I/O reads are completed normally. Bit Access & Default 31:0 R/W 00000000h MMIO Data Window Description Intel ® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet 203 §
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Intel ® 945G/945GZ/945GC/ 945P/945
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Contents 1 Introduction ...........
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4.2.11 C0DRC1—Channel A DRAM Cont
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6.1.16 DMICESTS—DMI Correctable E
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9.4.5 SMM Space Decode and Transact
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11.3 DC Characteristics ...........
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Revision History Rev Description Da
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Intel ® 82945G/82945GZ/82945GC/829
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1 Introduction Introduction The Int
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Figure 1-2. Intel ® 945GZ/82945GC
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1.1 Terminology Term Description Ac
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Term Description TOLM Top Of Low Me
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Introduction � Supports four bank
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Introduction 1.4 Graphics (Intel ®
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1.5 Analog and SDVO Displays (Intel
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2 Signal Description Signal Descrip
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2.1 Host Interface Signals Signal D
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Signal Name Type Description HREQ[4
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2.3 DDR2 DRAM Channel B Interface S
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Signal Description 2.6 Analog Displ
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2.8 Direct Media Interface (DMI) Si
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2.10 Power and Ground Name Voltage
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Interface Signal Name I/O System Me
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Interface Signal Name I/O State Dur
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3 Register Description Register Des
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Register Description Note: A physic
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3.3 Configuration Mechanisms Regist
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3.4 Routing Configuration Accesses
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3.4.2.2 DMI Configuration Accesses
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Bit Access & Default 10:8 R/W 000b
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Host Bridge/DRAM Controller Registe
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4.1 Device 0 Configuration Register
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4.1.4 PCISTS—PCI Status (D0:F0) P
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4.1.7 MLT—Master Latency Timer (D
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4.1.12 EPBAR—Egress Port Base Add
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4.1.19 PAM1—Programmable Attribut
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4.1.25 LAC—Legacy Access Control
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4.1.29 ERRSTS—Error Status (D0:F0
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4.1.31 SKPD—Scratchpad Data (D0:F
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4.2.7 C0DCLKDIS—Channel A DRAM Cl
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4.2.9 C0DRT1—Channel A DRAM Timin
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Bit Access & Default 6:4 R/W 000b 3
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4.2.24 PMSTS—Power Management Sta
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4.3.1 EPESD—EP Element Self Descr
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4.3.3 EPLE1A—EP Link Entry 1 Addr
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Host-PCI Express* Bridge Registers
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Address Offset Host-PCI Express* Br
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5.1.3 PCICMD1—PCI Command (D1:F0)
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5.1.4 PCISTS1—PCI Status (D1:F0)
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5.1.7 CL1—Cache Line Size (D1:F0)
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5.1.12 IOBASE1—I/O Base Address (
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5.1.15 MBASE1—Memory Base Address
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5.1.20 INTRLINE1—Interrupt Line (
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Bit Access & Default 2 R/W 0b 1 R/W
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5.1.29 MA—Message Address (D1:F0)
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5.1.33 DCAP—Device Capabilities (
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5.1.35 DSTS—Device Status (D1:F0)
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5.1.37 LCTL—Link Control (D1:F0)
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5.1.39 SLOTCAP—Slot Capabilities
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5.1.41 SLOTSTS—Slot Status (D1:F0
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5.1.43 RSTS—Root Status (D1:F0) P
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Page 151 and 152: Host-PCI Express* Bridge Registers
Page 153 and 154: 5.1.56 ESD—Element Self Descripti
Page 157 and 158: 5.1.61 CESTS—Correctable Error St
Page 161 and 162: Direct Media Interface (DMI) RCRB 6
Page 163 and 164: 6.1.3 DMIPVCCAP2—DMI Port VC Capa
Page 165 and 166: 6.1.6 DMIVC0RCTL—DMI VC0 Resource
Page 167 and 168: 6.1.9 DMIVC1RCTL—DMI VC1 Resource
Page 169 and 170: 6.1.13 DMILSTS—DMI Link Status MM
Page 171 and 172: 6.1.15 DMIUEMSK—DMI Uncorrectable
Page 173 and 174: Integrated Graphics Device (D2:F0)
Page 177 and 178: 7.1.4 PCISTS2—PCI Status (D2:F0)
Page 179 and 180: 7.1.7 CLS—Cache Line Size (D2:F0)
Page 181 and 182: 7.1.11 IOBAR—I/O Base Address (D2
Page 185 and 186: 7.1.20 MINGNT—Minimum Grant (D2:F
Page 193 and 194: 8.1.3 PCICMD2—PCI Command (D2:F1)
Page 195 and 196: 8.1.5 RID2—Revision Identificatio
Page 201: Integrated Graphics Device (D2:F1)
Page 205 and 206: 9 System Address Map System Address
Page 207 and 208: Figure 9-1. System Address Ranges 4
Page 209 and 210: Compatible SMRAM Address Range (A_0
Page 211 and 212: 9.2 Main Memory Address Range (1 MB
Page 213 and 214: 9.3 PCI Memory Address Range (TOLUD
Page 215 and 216: 9.3.6 PCI Express* Graphics Attach
Page 217 and 218: 9.4.1 SMM Space Definition System A
Page 219 and 220: 9.4.5 SMM Space Decode and Transact
Page 221 and 222: 9.4.12 Legacy VGA and I/O Range Dec
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Page 225 and 226: Interleaved Mode Functional Descrip
Page 227 and 228: 667 MHz (PC 5300) (82945G/82945GC/8
Page 229 and 230: 10.2.2.2 System Memory Supported Co
Page 231 and 232: Functional Description Table 10-5.
Page 233 and 234: 10.3 PCI Express* (Intel ® 82945G/
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Page 237 and 238: Figure 10-3. Concurrent SDVO / PCI
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Page 245 and 246: 10.5.4.8 Pixel Shader Functional De
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Functional Description device is in
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10.6.2 Digital Display Interface Fu
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10.6.2.1.5 Control Bus Functional D
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Figure 10-7 illustrates the various
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11 Electrical Characteristics Elect
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11.1.1 Power Characteristics Table
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Signal Group Electrical Characteris
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11.3 DC Characteristics Table 11-5.
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Symbol Signal Group Electrical Char
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Ballout and Package Information 12
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Ballout and Package Information Fig
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12.2 Ballout Table Ballout and Pack
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Ballout and Package Information EXP
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Ballout and Package Information HA2
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Ballout and Package Information HD6
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Ballout and Package Information RSV
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Ballout and Package Information SDM
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Ballout and Package Information SDQ
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Ballout and Package Information SDQ
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Ballout and Package Information VCC
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Ballout and Package Information VSS
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12.3 Package § Ballout and Package
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Ballout and Package Information Int
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13.2 XOR Test Mode Initialization T
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13.4 XOR Chains Testability Table 1
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Table 13-5. XOR Chain 2 Pin Count B
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Table 13-8. XOR Chain 5 Pin Count B
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Table 13-11. XOR Chain 8 Pin Count
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Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

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