Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL ® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel ® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH may contain design defects or errors known as errata, which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. 1 ® ® Hyper-Threading Technology requires a computer system with an Intel Pentium 4 processor supporting HT Technology and a Hyper-Threading Technology enabled chipset, BIOS and operating system. Performance will vary depending on the specific hardware and software you use. See http://www.intel.com/info/hyperthreading/ for more information including details on which processors support HT Technology. Intel and Pentium are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright © 2005-2008, Intel Corporation 2 Intel ® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
Contents 1 Introduction ....................................................................................................................... 17 1.1 Terminology .......................................................................................................... 21 1.2 Reference Documents .......................................................................................... 23 1.3 (G)MCH Overview ................................................................................................ 23 1.3.1 Host Interface ........................................................................................ 24 1.3.2 System Memory Interface ..................................................................... 24 1.3.3 Direct Media Interface (DMI) ................................................................. 25 1.3.4 PCI Express* Interface (Intel ® 82945G/82945GC/82945P/82945PL (G)MCH Only) ....................................................................................... 26 1.4 Graphics (Intel ® 82945G/82945GC/82945GZ GMCH Only) ................................ 27 1.5 Analog and SDVO Displays (Intel ® 82945G/82945GC/82945GZ GMCH Only) .. 29 1.5.1 System Interrupts .................................................................................. 29 1.5.2 (G)MCH Clocking .................................................................................. 29 1.5.3 Power Management .............................................................................. 30 2 Signal Description ............................................................................................................. 31 2.1 Host Interface Signals .......................................................................................... 33 2.2 DDR2 DRAM Channel A Interface ....................................................................... 36 2.3 DDR2 DRAM Channel B Interface ....................................................................... 37 2.4 DDR2 DRAM Reference and Compensation ....................................................... 38 2.5 PCI Express* Interface Signals (Intel ® 82945G/82945GC/82945P/82945PL Only) ..................................................................................................................... 38 2.6 Analog Display Signals (Intel ® 82945G/82945GC/ 82945GZ GMCH Only) ....... 39 2.7 Clocks, Reset, and Miscellaneous ....................................................................... 40 2.8 Direct Media Interface (DMI) ................................................................................ 41 2.9 Intel ® Serial DVO (SDVO) Interface (Intel ® 82945G/82945GC/82945GZ GMCH Only) ..................................................................................................................... 41 2.10 Power and Ground ............................................................................................... 43 2.11 Reset States and Pull-up/Pull-downs ................................................................... 44 3 Register Description .......................................................................................................... 49 3.1 Register Terminology ........................................................................................... 50 3.2 Platform Configuration .......................................................................................... 50 3.3 Configuration Mechanisms ................................................................................... 53 3.3.1 3.3.2 Standard PCI Configuration Mechanism .............................................. 53 PCI Express* Enhanced Configuration Mechanism (Intel ® 82945G/82945GC/82945P/82945PL (G)MCH Only) ........................... 53 3.4 Routing Configuration Accesses .......................................................................... 55 3.4.1 3.4.2 Internal Device Configuration Accesses ............................................... 56 Bridge Related Configuration Accesses ............................................... 56 3.4.2.1 PCI Express* Configuration Accesses (Intel ® 82945G/82945GC/82945P/82945PL (G)MCH Only) .......... 56 Intel ® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet 3
Page 1: Intel ® 945G/945GZ/945GC/ 945P/945
Page 5 and 6: 4.2.11 C0DRC1—Channel A DRAM Cont
Page 7 and 8: 6.1.16 DMICESTS—DMI Correctable E
Page 9 and 10: 9.4.5 SMM Space Decode and Transact
Page 11 and 12: 11.3 DC Characteristics ...........
Page 13 and 14: Revision History Rev Description Da
Page 15 and 16: Intel ® 82945G/82945GZ/82945GC/829
Page 17 and 18: 1 Introduction Introduction The Int
Page 19 and 20: Figure 1-2. Intel ® 945GZ/82945GC
Page 21 and 22: 1.1 Terminology Term Description Ac
Page 23 and 24: Term Description TOLM Top Of Low Me
Page 25 and 26: Introduction � Supports four bank
Page 27 and 28: Introduction 1.4 Graphics (Intel ®
Page 29 and 30: 1.5 Analog and SDVO Displays (Intel
Page 31 and 32: 2 Signal Description Signal Descrip
Page 33 and 34: 2.1 Host Interface Signals Signal D
Page 35 and 36: Signal Name Type Description HREQ[4
Page 37 and 38: 2.3 DDR2 DRAM Channel B Interface S
Page 39 and 40: Signal Description 2.6 Analog Displ
Page 41 and 42: 2.8 Direct Media Interface (DMI) Si
Page 43 and 44: 2.10 Power and Ground Name Voltage
Page 45 and 46: Interface Signal Name I/O System Me
Page 47 and 48: Interface Signal Name I/O State Dur
Page 49 and 50: 3 Register Description Register Des
Page 51 and 52: Register Description Note: A physic
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3.3 Configuration Mechanisms Regist
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3.4 Routing Configuration Accesses
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3.4.2.2 DMI Configuration Accesses
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Bit Access & Default 10:8 R/W 000b
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Host Bridge/DRAM Controller Registe
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4.1 Device 0 Configuration Register
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4.1.4 PCISTS—PCI Status (D0:F0) P
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4.1.7 MLT—Master Latency Timer (D
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4.1.12 EPBAR—Egress Port Base Add
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4.1.19 PAM1—Programmable Attribut
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4.1.25 LAC—Legacy Access Control
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4.1.29 ERRSTS—Error Status (D0:F0
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4.1.31 SKPD—Scratchpad Data (D0:F
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4.2.7 C0DCLKDIS—Channel A DRAM Cl
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4.2.9 C0DRT1—Channel A DRAM Timin
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Bit Access & Default 6:4 R/W 000b 3
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4.2.24 PMSTS—Power Management Sta
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4.3.1 EPESD—EP Element Self Descr
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4.3.3 EPLE1A—EP Link Entry 1 Addr
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Host-PCI Express* Bridge Registers
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Address Offset Host-PCI Express* Br
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5.1.3 PCICMD1—PCI Command (D1:F0)
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5.1.4 PCISTS1—PCI Status (D1:F0)
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5.1.7 CL1—Cache Line Size (D1:F0)
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5.1.12 IOBASE1—I/O Base Address (
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5.1.15 MBASE1—Memory Base Address
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5.1.20 INTRLINE1—Interrupt Line (
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Bit Access & Default 2 R/W 0b 1 R/W
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5.1.29 MA—Message Address (D1:F0)
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5.1.33 DCAP—Device Capabilities (
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5.1.35 DSTS—Device Status (D1:F0)
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5.1.37 LCTL—Link Control (D1:F0)
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5.1.39 SLOTCAP—Slot Capabilities
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5.1.41 SLOTSTS—Slot Status (D1:F0
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5.1.43 RSTS—Root Status (D1:F0) P
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5.1.56 ESD—Element Self Descripti
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5.1.61 CESTS—Correctable Error St
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Direct Media Interface (DMI) RCRB 6
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6.1.3 DMIPVCCAP2—DMI Port VC Capa
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6.1.6 DMIVC0RCTL—DMI VC0 Resource
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6.1.9 DMIVC1RCTL—DMI VC1 Resource
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6.1.13 DMILSTS—DMI Link Status MM
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6.1.15 DMIUEMSK—DMI Uncorrectable
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Integrated Graphics Device (D2:F0)
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7.1.4 PCISTS2—PCI Status (D2:F0)
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7.1.7 CLS—Cache Line Size (D2:F0)
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7.1.11 IOBAR—I/O Base Address (D2
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7.1.20 MINGNT—Minimum Grant (D2:F
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8.1.3 PCICMD2—PCI Command (D2:F1)
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8.1.5 RID2—Revision Identificatio
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8.2 Device 2 - PCI I/O Registers In
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9 System Address Map System Address
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Figure 9-1. System Address Ranges 4
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Compatible SMRAM Address Range (A_0
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9.2 Main Memory Address Range (1 MB
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9.3 PCI Memory Address Range (TOLUD
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9.3.6 PCI Express* Graphics Attach
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9.4.1 SMM Space Definition System A
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9.4.5 SMM Space Decode and Transact
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9.4.12 Legacy VGA and I/O Range Dec
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10 Functional Description This chap
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Interleaved Mode Functional Descrip
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667 MHz (PC 5300) (82945G/82945GC/8
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10.2.2.2 System Memory Supported Co
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Functional Description Table 10-5.
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10.3 PCI Express* (Intel ® 82945G/
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Figure 10-2. SDVO Conceptual Block
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Figure 10-3. Concurrent SDVO / PCI
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10.5 Integrated Graphics Device (In
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10.5.3 4X Faster Setup Engine Funct
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10.5.4 Texture Engine Functional De
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10.5.4.8 Pixel Shader Functional De
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Functional Description to determine
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10.5.6 2D Engine Functional Descrip
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10.5.8.1 Cursor Plane Functional De
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Functional Description device is in
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10.6.2 Digital Display Interface Fu
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10.6.2.1.5 Control Bus Functional D
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Figure 10-7 illustrates the various
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11 Electrical Characteristics Elect
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11.1.1 Power Characteristics Table
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Signal Group Electrical Characteris
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11.3 DC Characteristics Table 11-5.
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Symbol Signal Group Electrical Char
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Ballout and Package Information 12
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Ballout and Package Information Fig
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12.2 Ballout Table Ballout and Pack
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Ballout and Package Information EXP
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Ballout and Package Information HA2
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Ballout and Package Information HD6
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Ballout and Package Information RSV
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Ballout and Package Information SDM
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Ballout and Package Information SDQ
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Ballout and Package Information SDQ
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Ballout and Package Information VCC
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Ballout and Package Information VSS
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12.3 Package § Ballout and Package
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Ballout and Package Information Int
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13.2 XOR Test Mode Initialization T
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13.4 XOR Chains Testability Table 1
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Table 13-5. XOR Chain 2 Pin Count B
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Table 13-8. XOR Chain 5 Pin Count B
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Table 13-11. XOR Chain 8 Pin Count
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