Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

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Integrated Graphics Device (D2:F1) Registers (Intel® 82945G/82945GC/82945GZ GMCH Only) 8.1.4 PCISTS2—PCI Status (D2:F1) PCI Device: 2 Address Offset: 06h Default Value: 0090h Access: RO Size: 16 bits PCISTS2 reports the occurrence of a PCI compliant master abort and PCI compliant target abort. PCISTS2 also indicates the DEVSEL# timing that has been set by the IGD. Bit Access & Default 15 RO 0b 14 RO 0b 13 RO 0b 12 RO 0b 11 RO 0b 10:9 RO 00b 8 RO 0b 7 RO 1b 6 RO 0b 5 RO 0b 4 RO 1b 3 RO 0b 2:0 Reserved Description Detected Parity Error (DPE): Hardwired to 0. The IGD does not detect parity. Signaled System Error (SSE): Hardwired to 0. The IGD never asserts SERR#. Received Master Abort Status (RMAS): Hardwired to 0. The IGD never gets a master abort. Received Target Abort Status (RTAS): Hardwired to 0. The IGD never gets a target abort. Signaled Target Abort Status (STAS): Hardwired to 0. The IGD does not use target abort semantics. DEVSEL Timing (DEVT): N/A. Hardwired to 00. Master Data Parity Error Detected (DPD): Hardwired to 0. Since Parity Error Response is hardwired to disabled (and the IGD does not do any parity detection), this bit is hardwired to 0. Fast Back-to-Back (FB2B): Hardwired to 1. The IGD accepts fast back-to-back when the transactions are not to the same agent. User Defined Format (UDF): Hardwired to 0. 66 MHz PCI Capable (66C): Hardwired to 0. Capability List (CLIST): This bit is hardwired to 1 to indicate that the register at 34h provides an offset into the function’s PCI configuration space containing a pointer to the location of the first item in the list. Interrupt Status: Hardwired to 0. 194 Intel ® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
8.1.5 RID2—Revision Identification (D2:F1) PCI Device: 2 Address Offset: 08h Default Value: See bit description Access: RO Size: 8 bits Integrated Graphics Device (D2:F1) Registers (Intel® 82945G/82945GC/82945GZ GMCH Only) This register is a copy of Device 2, Function 0. It has the same read, write attributes as Function 0. It is implemented as common hardware with two access addresses. Bit Access & Default Description 7:0 RO Revision Identification Number (RID): This is an 8-bit value that indicates the revision identification number for the GMCH. Refer to the Intel ® 945G/945GC/945GZ/945P/945PL Express Chipset Specification Update for the value of the Revision ID register. 8.1.6 CC—Class Code Register (D2:F1) PCI Device: 2 Address Offset: 09h Default Value: 038000h Access: RO Size: 24 bits This register contains the device programming interface information related to the Sub-Class Code and Base Class Code definition for the IGD. This register also contains the Base Class Code and the function sub-class in relation to the Base Class Code. Bit Access & Default 23:16 RO 03h 15:8 RO 80h 7:0 RO 00h Description Base Class Code (BCC): This is an 8-bit value that indicates the base class code for the GMCH. 03h = Display controller. Sub-Class Code (SUBCC): 80h = Non VGA Programming Interface (PI): 00h = Display controller. Intel ® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet 195
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Intel ® 945G/945GZ/945GC/ 945P/945
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Contents 1 Introduction ...........
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4.2.11 C0DRC1—Channel A DRAM Cont
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6.1.16 DMICESTS—DMI Correctable E
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9.4.5 SMM Space Decode and Transact
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11.3 DC Characteristics ...........
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Revision History Rev Description Da
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Intel ® 82945G/82945GZ/82945GC/829
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1 Introduction Introduction The Int
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Figure 1-2. Intel ® 945GZ/82945GC
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1.1 Terminology Term Description Ac
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Term Description TOLM Top Of Low Me
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Introduction � Supports four bank
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Introduction 1.4 Graphics (Intel ®
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1.5 Analog and SDVO Displays (Intel
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2 Signal Description Signal Descrip
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2.1 Host Interface Signals Signal D
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Signal Name Type Description HREQ[4
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2.3 DDR2 DRAM Channel B Interface S
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Signal Description 2.6 Analog Displ
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2.8 Direct Media Interface (DMI) Si
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2.10 Power and Ground Name Voltage
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Interface Signal Name I/O System Me
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Interface Signal Name I/O State Dur
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3 Register Description Register Des
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Register Description Note: A physic
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3.3 Configuration Mechanisms Regist
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3.4 Routing Configuration Accesses
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3.4.2.2 DMI Configuration Accesses
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Bit Access & Default 10:8 R/W 000b
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Host Bridge/DRAM Controller Registe
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4.1 Device 0 Configuration Register
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4.1.4 PCISTS—PCI Status (D0:F0) P
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4.1.7 MLT—Master Latency Timer (D
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4.1.12 EPBAR—Egress Port Base Add
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4.1.19 PAM1—Programmable Attribut
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4.1.25 LAC—Legacy Access Control
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4.1.29 ERRSTS—Error Status (D0:F0
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4.1.31 SKPD—Scratchpad Data (D0:F
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4.2.7 C0DCLKDIS—Channel A DRAM Cl
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4.2.9 C0DRT1—Channel A DRAM Timin
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Bit Access & Default 6:4 R/W 000b 3
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4.2.24 PMSTS—Power Management Sta
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4.3.1 EPESD—EP Element Self Descr
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4.3.3 EPLE1A—EP Link Entry 1 Addr
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Host-PCI Express* Bridge Registers
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Address Offset Host-PCI Express* Br
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5.1.3 PCICMD1—PCI Command (D1:F0)
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5.1.4 PCISTS1—PCI Status (D1:F0)
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5.1.7 CL1—Cache Line Size (D1:F0)
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5.1.12 IOBASE1—I/O Base Address (
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5.1.15 MBASE1—Memory Base Address
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5.1.20 INTRLINE1—Interrupt Line (
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Bit Access & Default 2 R/W 0b 1 R/W
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5.1.29 MA—Message Address (D1:F0)
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5.1.33 DCAP—Device Capabilities (
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5.1.35 DSTS—Device Status (D1:F0)
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5.1.37 LCTL—Link Control (D1:F0)
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5.1.39 SLOTCAP—Slot Capabilities
Page 143 and 144: 5.1.41 SLOTSTS—Slot Status (D1:F0
Page 145 and 146: 5.1.43 RSTS—Root Status (D1:F0) P
Page 147 and 148: Host-PCI Express* Bridge Registers
Page 153 and 154: 5.1.56 ESD—Element Self Descripti
Page 157 and 158: 5.1.61 CESTS—Correctable Error St
Page 161 and 162: Direct Media Interface (DMI) RCRB 6
Page 163 and 164: 6.1.3 DMIPVCCAP2—DMI Port VC Capa
Page 165 and 166: 6.1.6 DMIVC0RCTL—DMI VC0 Resource
Page 167 and 168: 6.1.9 DMIVC1RCTL—DMI VC1 Resource
Page 169 and 170: 6.1.13 DMILSTS—DMI Link Status MM
Page 171 and 172: 6.1.15 DMIUEMSK—DMI Uncorrectable
Page 173 and 174: Integrated Graphics Device (D2:F0)
Page 177 and 178: 7.1.4 PCISTS2—PCI Status (D2:F0)
Page 179 and 180: 7.1.7 CLS—Cache Line Size (D2:F0)
Page 181 and 182: 7.1.11 IOBAR—I/O Base Address (D2
Page 185 and 186: 7.1.20 MINGNT—Minimum Grant (D2:F
Page 193: 8.1.3 PCICMD2—PCI Command (D2:F1)
Page 203 and 204: 8.2 Device 2 - PCI I/O Registers In
Page 205 and 206: 9 System Address Map System Address
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Page 209 and 210: Compatible SMRAM Address Range (A_0
Page 211 and 212: 9.2 Main Memory Address Range (1 MB
Page 213 and 214: 9.3 PCI Memory Address Range (TOLUD
Page 215 and 216: 9.3.6 PCI Express* Graphics Attach
Page 217 and 218: 9.4.1 SMM Space Definition System A
Page 219 and 220: 9.4.5 SMM Space Decode and Transact
Page 221 and 222: 9.4.12 Legacy VGA and I/O Range Dec
Page 223 and 224: 10 Functional Description This chap
Page 225 and 226: Interleaved Mode Functional Descrip
Page 227 and 228: 667 MHz (PC 5300) (82945G/82945GC/8
Page 229 and 230: 10.2.2.2 System Memory Supported Co
Page 231 and 232: Functional Description Table 10-5.
Page 233 and 234: 10.3 PCI Express* (Intel ® 82945G/
Page 235 and 236: Figure 10-2. SDVO Conceptual Block
Page 237 and 238: Figure 10-3. Concurrent SDVO / PCI
Page 239 and 240: 10.5 Integrated Graphics Device (In
Page 241 and 242: 10.5.3 4X Faster Setup Engine Funct
Page 243 and 244: 10.5.4 Texture Engine Functional De
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10.5.4.8 Pixel Shader Functional De
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Functional Description to determine
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10.5.6 2D Engine Functional Descrip
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10.5.8.1 Cursor Plane Functional De
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Functional Description device is in
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10.6.2 Digital Display Interface Fu
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10.6.2.1.5 Control Bus Functional D
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Figure 10-7 illustrates the various
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11 Electrical Characteristics Elect
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11.1.1 Power Characteristics Table
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Signal Group Electrical Characteris
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11.3 DC Characteristics Table 11-5.
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Symbol Signal Group Electrical Char
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Ballout and Package Information 12
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Ballout and Package Information Fig
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12.2 Ballout Table Ballout and Pack
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Ballout and Package Information EXP
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Ballout and Package Information HA2
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Ballout and Package Information HD6
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Ballout and Package Information RSV
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Ballout and Package Information SDM
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Ballout and Package Information SDQ
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Ballout and Package Information SDQ
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Ballout and Package Information VCC
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Ballout and Package Information VSS
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12.3 Package § Ballout and Package
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Ballout and Package Information Int
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13.2 XOR Test Mode Initialization T
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13.4 XOR Chains Testability Table 1
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Table 13-5. XOR Chain 2 Pin Count B
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Table 13-8. XOR Chain 5 Pin Count B
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Table 13-11. XOR Chain 8 Pin Count
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Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

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