Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

Integrated Graphics Device (D2:F0) (Intel® 82945G/82945GC/ 82945GZ GMCH Only)
7.1.29 PMCS—Power Management Control/Status (D2:F0)
PCI Device: 2
Address Offset: D4h
Default Value: 0000h
Access: RO, R/W
Size: 16 bits
Bit Access &
Default
15 RO
0b
14:9 Reserved
8 RO
0b
7:2 Reserved
1:0 R/W
00b
Description
PME_Status: This bit is 0 to indicate that the IGD does not support PME#
generation from D3 (cold).
PME_En: This bit is 0 to indicate that PME# assertion from D3 (cold) is disabled.
Power State: This field indicates the current power state of the IGD and can be
used to set the IGD into a new power state. If software attempts to write an
unsupported state to this field, the write operation must complete normally on the
bus, but the data is discarded and no state change occurs.
On a transition from D3 to D0 the graphics controller is optionally reset to initial
values. Behavior of the graphics controller in supported states is detailed in the
power management section.
00 = D0 (Default)
01 = D1 (Not Supported)
10 = D2 (Not Supported)
11 = D3
7.1.30 SWSMI—Software SMI (D2:F0)
PCI Device: 2
Address Offset: E0h
Default Value: 0000h
Access: R/W
Size: 16 bits
As long as there is the potential that DVO port legacy drivers exist that expect this register at this
address, D2, F0, address E0h–E1h must be reserved for this register.
Bit Access &
Default
15:8 R/W
00h
7:1 R/W
00h
0 R/W
0b
SW scratch bits
Description
Software Flag: This field indicates the caller and SMI function desired, as well
as return result.
GMCH Software SMI Event: Software must write a 0 to clear this bit.
0 = SMI Not triggered.
1 = When set, this bit will trigger an SMI.
188 Intel ® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet