Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

More documents

Recommendations

Info

Integrated Graphics Device (D2:F0) (Intel® 82945G/82945GC/ 82945GZ GMCH Only) 7.1.24 MGGC—Mirror of Device 0 GMCH Graphics Control (D2:F0) (Mirrored_D0_52) PCI Device: 2 Address Offset: 52h Default Value: 0030h Access: RO Size: 16 bits This register is a read only copy of Device 0, offset 52h register. 7.1.25 MDEVEN—Mirror of Device 0 Device Enable (D2:F0) (Mirrored_D0_54) PCI Device: 2 Address Offset: 54h Default Value: 82945G/82945GC/82945GZ GMCH: 0000001Bh 82945P/82945PL MCH: 00000003h Access: RO Size: 32 bits This register is a read only copy of Device 0, Function 0, offset 54h register. 7.1.26 BSM—Base of “Stolen” Memory (D2:F0) PCI Device: 2 Address Offset: 5Ch Default Value: 07800000h Access: RO Size: 32 bits Graphics Stolen Memory and TSEG are within DRAM space defined under TOLUD. From the top of low used DRAM, the GMCH claims 1 to 64 MBs of DRAM for internal graphics if enabled. Bit Access & Default 31:20 RO 078h 19:0 Reserved Description Base of Stolen Memory (BSM): This register contains bits 31:20 of the base address of stolen DRAM memory. The host interface determines the base of graphics stolen memory by subtracting the graphics stolen memory size from TOLUD. See Device 0 TOLUD for more explanation. 186 Intel ® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
Integrated Graphics Device (D2:F0) (Intel® 82945G/82945GC/ 82945GZ GMCH Only) 7.1.27 PMCAPID—Power Management Capabilities ID (D2:F0) PCI Device: 2 Address Offset: D0h Default Value: 0001h Access: RO Size: 16 bits Bit Access & Default 15:8 RO 00h 7:0 RO 01h Description NEXT_PTR: This field contains a pointer to the next item in the capabilities list. This is the final capability in the list and must be set to 00h. CAP_ID: SIG defines this ID is 01h for power management. 7.1.28 PMCAP—Power Management Capabilities (D2:F0) PCI Device: 2 Address Offset: D2h Default Value: 0022h Access: RO Size: 16 bits Bit Access & Default 15:11 RO 00h 10 RO 0b 9 RO 0b 8:6 Reserved 5 RO 1b 4 RO 0b 3 RO 0b 2:0 RO 010b Description PME Support: This field indicates the power states in which the IGD may assert PME#. The field is hardwired to 0s to indicate that the IGD does not assert the PME# signal. D2: Hardwired to 0 to indicate that the D2 power management state is not supported. D1: Hardwired to 0 to indicate that the D1 power management state is not supported. Device Specific Initialization (DSI): Hardwired to 1 to indicate that special initialization of the IGD is required before generic class device driver is to use it. Auxiliary Power Source: Hardwired to 0. PME Clock: Hardwired to 0 to indicate IGD does not support PME# generation. Version: Hardwired to 010b to indicate that there are 4 bytes of power management registers implemented and that this device complies with the PCI Power Management Interface Specification, Revision 1.1. Intel ® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet 187
Page 1 and 2:
Intel ® 945G/945GZ/945GC/ 945P/945
Page 3 and 4:
Contents 1 Introduction ...........
Page 5 and 6:
4.2.11 C0DRC1—Channel A DRAM Cont
Page 7 and 8:
6.1.16 DMICESTS—DMI Correctable E
Page 9 and 10:
9.4.5 SMM Space Decode and Transact
Page 11 and 12:
11.3 DC Characteristics ...........
Page 13 and 14:
Revision History Rev Description Da
Page 15 and 16:
Intel ® 82945G/82945GZ/82945GC/829
Page 17 and 18:
1 Introduction Introduction The Int
Page 19 and 20:
Figure 1-2. Intel ® 945GZ/82945GC
Page 21 and 22:
1.1 Terminology Term Description Ac
Page 23 and 24:
Term Description TOLM Top Of Low Me
Page 25 and 26:
Introduction � Supports four bank
Page 27 and 28:
Introduction 1.4 Graphics (Intel ®
Page 29 and 30:
1.5 Analog and SDVO Displays (Intel
Page 31 and 32:
2 Signal Description Signal Descrip
Page 33 and 34:
2.1 Host Interface Signals Signal D
Page 35 and 36:
Signal Name Type Description HREQ[4
Page 37 and 38:
2.3 DDR2 DRAM Channel B Interface S
Page 39 and 40:
Signal Description 2.6 Analog Displ
Page 41 and 42:
2.8 Direct Media Interface (DMI) Si
Page 43 and 44:
2.10 Power and Ground Name Voltage
Page 45 and 46:
Interface Signal Name I/O System Me
Page 47 and 48:
Interface Signal Name I/O State Dur
Page 49 and 50:
3 Register Description Register Des
Page 51 and 52:
Register Description Note: A physic
Page 53 and 54:
3.3 Configuration Mechanisms Regist
Page 55 and 56:
3.4 Routing Configuration Accesses
Page 57 and 58:
3.4.2.2 DMI Configuration Accesses
Page 59 and 60:
Bit Access & Default 10:8 R/W 000b
Page 61 and 62:
Host Bridge/DRAM Controller Registe
Page 63 and 64:
4.1 Device 0 Configuration Register
Page 65 and 66:
4.1.4 PCISTS—PCI Status (D0:F0) P
Page 67 and 68:
4.1.7 MLT—Master Latency Timer (D
Page 69 and 70:
4.1.12 EPBAR—Egress Port Base Add
Page 71 and 72:
Page 73 and 74:
Page 75 and 76:
Page 77 and 78:
4.1.19 PAM1—Programmable Attribut
Page 79 and 80:
Page 81 and 82:
Page 83 and 84:
4.1.25 LAC—Legacy Access Control
Page 85 and 86:
Page 87 and 88:
4.1.29 ERRSTS—Error Status (D0:F0
Page 89 and 90:
4.1.31 SKPD—Scratchpad Data (D0:F
Page 91 and 92:
Page 93 and 94:
Page 95 and 96:
4.2.7 C0DCLKDIS—Channel A DRAM Cl
Page 97 and 98:
4.2.9 C0DRT1—Channel A DRAM Timin
Page 99 and 100:
Bit Access & Default 6:4 R/W 000b 3
Page 101 and 102:
Page 103 and 104:
4.2.24 PMSTS—Power Management Sta
Page 105 and 106:
4.3.1 EPESD—EP Element Self Descr
Page 107 and 108:
4.3.3 EPLE1A—EP Link Entry 1 Addr
Page 109 and 110:
Host-PCI Express* Bridge Registers
Page 111 and 112:
Address Offset Host-PCI Express* Br
Page 113 and 114:
5.1.3 PCICMD1—PCI Command (D1:F0)
Page 115 and 116:
5.1.4 PCISTS1—PCI Status (D1:F0)
Page 117 and 118:
5.1.7 CL1—Cache Line Size (D1:F0)
Page 119 and 120:
5.1.12 IOBASE1—I/O Base Address (
Page 121 and 122:
5.1.15 MBASE1—Memory Base Address
Page 123 and 124:
Page 125 and 126:
5.1.20 INTRLINE1—Interrupt Line (
Page 127 and 128:
Bit Access & Default 2 R/W 0b 1 R/W
Page 129 and 130:
Page 131 and 132:
Page 133 and 134:
5.1.29 MA—Message Address (D1:F0)
Page 135 and 136: 5.1.33 DCAP—Device Capabilities (
Page 137 and 138: 5.1.35 DSTS—Device Status (D1:F0)
Page 139 and 140: 5.1.37 LCTL—Link Control (D1:F0)
Page 141 and 142: 5.1.39 SLOTCAP—Slot Capabilities
Page 143 and 144: 5.1.41 SLOTSTS—Slot Status (D1:F0
Page 145 and 146: 5.1.43 RSTS—Root Status (D1:F0) P
Page 147 and 148: Host-PCI Express* Bridge Registers
Page 153 and 154: 5.1.56 ESD—Element Self Descripti
Page 157 and 158: 5.1.61 CESTS—Correctable Error St
Page 161 and 162: Direct Media Interface (DMI) RCRB 6
Page 163 and 164: 6.1.3 DMIPVCCAP2—DMI Port VC Capa
Page 165 and 166: 6.1.6 DMIVC0RCTL—DMI VC0 Resource
Page 167 and 168: 6.1.9 DMIVC1RCTL—DMI VC1 Resource
Page 169 and 170: 6.1.13 DMILSTS—DMI Link Status MM
Page 171 and 172: 6.1.15 DMIUEMSK—DMI Uncorrectable
Page 173 and 174: Integrated Graphics Device (D2:F0)
Page 177 and 178: 7.1.4 PCISTS2—PCI Status (D2:F0)
Page 179 and 180: 7.1.7 CLS—Cache Line Size (D2:F0)
Page 181 and 182: 7.1.11 IOBAR—I/O Base Address (D2
Page 185: 7.1.20 MINGNT—Minimum Grant (D2:F
Page 193 and 194: 8.1.3 PCICMD2—PCI Command (D2:F1)
Page 195 and 196: 8.1.5 RID2—Revision Identificatio
Page 203 and 204: 8.2 Device 2 - PCI I/O Registers In
Page 205 and 206: 9 System Address Map System Address
Page 207 and 208: Figure 9-1. System Address Ranges 4
Page 209 and 210: Compatible SMRAM Address Range (A_0
Page 211 and 212: 9.2 Main Memory Address Range (1 MB
Page 213 and 214: 9.3 PCI Memory Address Range (TOLUD
Page 215 and 216: 9.3.6 PCI Express* Graphics Attach
Page 217 and 218: 9.4.1 SMM Space Definition System A
Page 219 and 220: 9.4.5 SMM Space Decode and Transact
Page 221 and 222: 9.4.12 Legacy VGA and I/O Range Dec
Page 223 and 224: 10 Functional Description This chap
Page 225 and 226: Interleaved Mode Functional Descrip
Page 227 and 228: 667 MHz (PC 5300) (82945G/82945GC/8
Page 229 and 230: 10.2.2.2 System Memory Supported Co
Page 231 and 232: Functional Description Table 10-5.
Page 233 and 234: 10.3 PCI Express* (Intel ® 82945G/
Page 235 and 236: Figure 10-2. SDVO Conceptual Block
Page 237 and 238:
Figure 10-3. Concurrent SDVO / PCI
Page 239 and 240:
10.5 Integrated Graphics Device (In
Page 241 and 242:
10.5.3 4X Faster Setup Engine Funct
Page 243 and 244:
10.5.4 Texture Engine Functional De
Page 245 and 246:
10.5.4.8 Pixel Shader Functional De
Page 247 and 248:
Functional Description to determine
Page 249 and 250:
10.5.6 2D Engine Functional Descrip
Page 251 and 252:
10.5.8.1 Cursor Plane Functional De
Page 253 and 254:
Functional Description device is in
Page 255 and 256:
10.6.2 Digital Display Interface Fu
Page 257 and 258:
10.6.2.1.5 Control Bus Functional D
Page 259 and 260:
Figure 10-7 illustrates the various
Page 261 and 262:
11 Electrical Characteristics Elect
Page 263 and 264:
11.1.1 Power Characteristics Table
Page 265 and 266:
Signal Group Electrical Characteris
Page 267 and 268:
11.3 DC Characteristics Table 11-5.
Page 269 and 270:
Symbol Signal Group Electrical Char
Page 271 and 272:
Ballout and Package Information 12
Page 273 and 274:
Ballout and Package Information Fig
Page 275 and 276:
12.2 Ballout Table Ballout and Pack
Page 277 and 278:
Ballout and Package Information EXP
Page 279 and 280:
Ballout and Package Information HA2
Page 281 and 282:
Ballout and Package Information HD6
Page 283 and 284:
Ballout and Package Information RSV
Page 285 and 286:
Ballout and Package Information SDM
Page 287 and 288:
Ballout and Package Information SDQ
Page 289 and 290:
Ballout and Package Information SDQ
Page 291 and 292:
Ballout and Package Information VCC
Page 293 and 294:
Page 295 and 296:
Page 297 and 298:
Ballout and Package Information VSS
Page 299 and 300:
Page 301 and 302:
Page 303 and 304:
Page 305 and 306:
12.3 Package § Ballout and Package
Page 307 and 308:
Ballout and Package Information Int
Page 309 and 310:
13.2 XOR Test Mode Initialization T
Page 311 and 312:
13.4 XOR Chains Testability Table 1
Page 313 and 314:
Table 13-5. XOR Chain 2 Pin Count B
Page 315 and 316:
Table 13-8. XOR Chain 5 Pin Count B
Page 317 and 318:
Table 13-11. XOR Chain 8 Pin Count
show all

Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

Create successful ePaper yourself

Delete template?

Save as template?