Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...
Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ... Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...
Integrated Graphics Device (D2:F0) (Intel® 82945G/82945GC/ 82945GZ GMCH Only) 7.1.24 MGGC—Mirror of Device 0 GMCH Graphics Control (D2:F0) (Mirrored_D0_52) PCI Device: 2 Address Offset: 52h Default Value: 0030h Access: RO Size: 16 bits This register is a read only copy of Device 0, offset 52h register. 7.1.25 MDEVEN—Mirror of Device 0 Device Enable (D2:F0) (Mirrored_D0_54) PCI Device: 2 Address Offset: 54h Default Value: 82945G/82945GC/82945GZ GMCH: 0000001Bh 82945P/82945PL MCH: 00000003h Access: RO Size: 32 bits This register is a read only copy of Device 0, Function 0, offset 54h register. 7.1.26 BSM—Base of “Stolen” Memory (D2:F0) PCI Device: 2 Address Offset: 5Ch Default Value: 07800000h Access: RO Size: 32 bits Graphics Stolen Memory and TSEG are within DRAM space defined under TOLUD. From the top of low used DRAM, the GMCH claims 1 to 64 MBs of DRAM for internal graphics if enabled. Bit Access & Default 31:20 RO 078h 19:0 Reserved Description Base of Stolen Memory (BSM): This register contains bits 31:20 of the base address of stolen DRAM memory. The host interface determines the base of graphics stolen memory by subtracting the graphics stolen memory size from TOLUD. See Device 0 TOLUD for more explanation. 186 Intel ® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
Integrated Graphics Device (D2:F0) (Intel® 82945G/82945GC/ 82945GZ GMCH Only) 7.1.27 PMCAPID—Power Management Capabilities ID (D2:F0) PCI Device: 2 Address Offset: D0h Default Value: 0001h Access: RO Size: 16 bits Bit Access & Default 15:8 RO 00h 7:0 RO 01h Description NEXT_PTR: This field contains a pointer to the next item in the capabilities list. This is the final capability in the list and must be set to 00h. CAP_ID: SIG defines this ID is 01h for power management. 7.1.28 PMCAP—Power Management Capabilities (D2:F0) PCI Device: 2 Address Offset: D2h Default Value: 0022h Access: RO Size: 16 bits Bit Access & Default 15:11 RO 00h 10 RO 0b 9 RO 0b 8:6 Reserved 5 RO 1b 4 RO 0b 3 RO 0b 2:0 RO 010b Description PME Support: This field indicates the power states in which the IGD may assert PME#. The field is hardwired to 0s to indicate that the IGD does not assert the PME# signal. D2: Hardwired to 0 to indicate that the D2 power management state is not supported. D1: Hardwired to 0 to indicate that the D1 power management state is not supported. Device Specific Initialization (DSI): Hardwired to 1 to indicate that special initialization of the IGD is required before generic class device driver is to use it. Auxiliary Power Source: Hardwired to 0. PME Clock: Hardwired to 0 to indicate IGD does not support PME# generation. Version: Hardwired to 010b to indicate that there are 4 bytes of power management registers implemented and that this device complies with the PCI Power Management Interface Specification, Revision 1.1. Intel ® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet 187
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- Page 137 and 138: 5.1.35 DSTS—Device Status (D1:F0)
- Page 139 and 140: 5.1.37 LCTL—Link Control (D1:F0)
- Page 141 and 142: 5.1.39 SLOTCAP—Slot Capabilities
- Page 143 and 144: 5.1.41 SLOTSTS—Slot Status (D1:F0
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- Page 161 and 162: Direct Media Interface (DMI) RCRB 6
- Page 163 and 164: 6.1.3 DMIPVCCAP2—DMI Port VC Capa
- Page 165 and 166: 6.1.6 DMIVC0RCTL—DMI VC0 Resource
- Page 167 and 168: 6.1.9 DMIVC1RCTL—DMI VC1 Resource
- Page 169 and 170: 6.1.13 DMILSTS—DMI Link Status MM
- Page 171 and 172: 6.1.15 DMIUEMSK—DMI Uncorrectable
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- Page 179 and 180: 7.1.7 CLS—Cache Line Size (D2:F0)
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- Page 205 and 206: 9 System Address Map System Address
- Page 207 and 208: Figure 9-1. System Address Ranges 4
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- Page 211 and 212: 9.2 Main Memory Address Range (1 MB
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- Page 217 and 218: 9.4.1 SMM Space Definition System A
- Page 219 and 220: 9.4.5 SMM Space Decode and Transact
- Page 221 and 222: 9.4.12 Legacy VGA and I/O Range Dec
- Page 223 and 224: 10 Functional Description This chap
- Page 225 and 226: Interleaved Mode Functional Descrip
- Page 227 and 228: 667 MHz (PC 5300) (82945G/82945GC/8
- Page 229 and 230: 10.2.2.2 System Memory Supported Co
- Page 231 and 232: Functional Description Table 10-5.
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- Page 235 and 236: Figure 10-2. SDVO Conceptual Block
Integrated Graphics Device (D2:F0) (<strong>Intel®</strong> 82<strong>945G</strong>/82<strong>945G</strong>C/ 82<strong>945G</strong>Z GMCH Only)<br />
7.1.24 MGGC—Mirror of Device 0 GMCH Graphics Control (D2:F0)<br />
(Mirrored_D0_52)<br />
PCI Device: 2<br />
Address Offset: 52h<br />
Default Value: 0030h<br />
Access: RO<br />
Size: 16 bits<br />
This register is a read only copy of Device 0, offset 52h register.<br />
7.1.25 MDEVEN—Mirror of Device 0 Device Enable (D2:F0)<br />
(Mirrored_D0_54)<br />
PCI Device: 2<br />
Address Offset: 54h<br />
Default Value: 82<strong>945G</strong>/82<strong>945G</strong>C/82<strong>945G</strong>Z GMCH: 0000001Bh<br />
82<strong>945P</strong>/82<strong>945P</strong>L MCH: 00000003h<br />
Access: RO<br />
Size: 32 bits<br />
This register is a read only copy of Device 0, Function 0, offset 54h register.<br />
7.1.26 BSM—Base of “Stolen” Memory (D2:F0)<br />
PCI Device: 2<br />
Address Offset: 5Ch<br />
Default Value: 07800000h<br />
Access: RO<br />
Size: 32 bits<br />
Graphics Stolen Memory and TSEG are within DRAM space defined under TOLUD. From the<br />
top of low used DRAM, the GMCH claims 1 to 64 MBs of DRAM for internal graphics if<br />
enabled.<br />
Bit Access &<br />
Default<br />
31:20 RO<br />
078h<br />
19:0 Reserved<br />
Description<br />
Base of Stolen Memory (BSM): This register contains bits 31:20 of the base<br />
address of stolen DRAM memory. The host interface determines the base of<br />
graphics stolen memory by subtracting the graphics stolen memory size from<br />
TOLUD. See Device 0 TOLUD for more explanation.<br />
186 Intel ® 82<strong>945G</strong>/82<strong>945G</strong>Z/82<strong>945G</strong>C GMCH and 82<strong>945P</strong>/82<strong>945P</strong>L MCH Datasheet
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