Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...
Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ... Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...
Integrated Graphics Device (D2:F0) (Intel® 82945G/82945GC/ 82945GZ GMCH Only) 7.1.17 CAPPOINT—Capabilities Pointer (D2:F0) PCI Device: 2 Address Offset: 34h Default Value: 90h Access: RO Size: 8 bits Bit Access & Default 7:0 RO 90h 7.1.18 INTRLINE—Interrupt Line (D2:F0) PCI Device: 2 Address Offset: 3Ch Default Value: 01h Access: R/W Size: 8 bits Bit Access & Default 7:0 R/W 01h 7.1.19 INTRPIN—Interrupt Pin (D2:F0) PCI Device: 2 Address Offset: 3Dh Default Value: 01h Access: RO Size: 8 bits Bit Access & Default 7:0 RO 01h Description Capabilities Pointer Value: This field contains an offset into the function’s PCI configuration space for the first item in the New Capabilities Linked List, the MSI Capabilities ID registers at address 90h, or the Power Management Capabilities ID registers at address D0h. Description Interrupt Connection: This field is used to communicate interrupt line routing information. POST software writes the routing information into this register as it initializes and configures the system. The value in this register indicates which input of the system interrupt controller that is connected to the device’s interrupt pin. Description Interrupt Pin: As a device that only has interrupts associated with a single function, the IGD specifies INTA# as its interrupt pin. 01h = INTA#. 184 Intel ® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
7.1.20 MINGNT—Minimum Grant (D2:F0) PCI Device: 2 Address Offset: 3Eh Default Value: 00h Access: RO Size: 8 bits Bit Access & Default 7:0 RO 00h Integrated Graphics Device (D2:F0) (Intel® 82945G/82945GC/ 82945GZ GMCH Only) Description Minimum Grant Value: The IGD does not burst as a PCI compliant master. 7.1.21 MAXLAT—Maximum Latency (D2:F0) PCI Device: 2 Address Offset: 3Fh Default Value: 00h Access: RO Size: 8 bits Bit Access & Default 7:0 RO 00h Description Maximum Latency Value: The IGD has no specific requirements for how often it needs to access the PCI bus. 7.1.22 MCAPPTR—Mirror of Device 0 Capability Pointer (D2:F0) (Mirrored_D0_34) PCI Device: 2 Address Offset: 44h Default Value: E0h Access: RO Size: 8 bits This register is a read only copy of Device 0, offset 34h register. 7.1.23 MCAPID—Mirror of Device 0 Capability Identification (D2:F0) (Mirrored_D0_E0) PCI Device: 2 Address Offset: 48h Default Value: 000000000001090009h Access: RO Size: 72 bits This register is a read only copy of Device 0, offset E0h register. Intel ® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet 185
- Page 133 and 134: 5.1.29 MA—Message Address (D1:F0)
- Page 135 and 136: 5.1.33 DCAP—Device Capabilities (
- Page 137 and 138: 5.1.35 DSTS—Device Status (D1:F0)
- Page 139 and 140: 5.1.37 LCTL—Link Control (D1:F0)
- Page 141 and 142: 5.1.39 SLOTCAP—Slot Capabilities
- Page 143 and 144: 5.1.41 SLOTSTS—Slot Status (D1:F0
- Page 145 and 146: 5.1.43 RSTS—Root Status (D1:F0) P
- Page 147 and 148: Host-PCI Express* Bridge Registers
- Page 149 and 150: Host-PCI Express* Bridge Registers
- Page 151 and 152: Host-PCI Express* Bridge Registers
- Page 153 and 154: 5.1.56 ESD—Element Self Descripti
- Page 155 and 156: Host-PCI Express* Bridge Registers
- Page 157 and 158: 5.1.61 CESTS—Correctable Error St
- Page 159 and 160: Host-PCI Express* Bridge Registers
- Page 161 and 162: Direct Media Interface (DMI) RCRB 6
- Page 163 and 164: 6.1.3 DMIPVCCAP2—DMI Port VC Capa
- Page 165 and 166: 6.1.6 DMIVC0RCTL—DMI VC0 Resource
- Page 167 and 168: 6.1.9 DMIVC1RCTL—DMI VC1 Resource
- Page 169 and 170: 6.1.13 DMILSTS—DMI Link Status MM
- Page 171 and 172: 6.1.15 DMIUEMSK—DMI Uncorrectable
- Page 173 and 174: Integrated Graphics Device (D2:F0)
- Page 175 and 176: Integrated Graphics Device (D2:F0)
- Page 177 and 178: 7.1.4 PCISTS2—PCI Status (D2:F0)
- Page 179 and 180: 7.1.7 CLS—Cache Line Size (D2:F0)
- Page 181 and 182: 7.1.11 IOBAR—I/O Base Address (D2
- Page 183: Integrated Graphics Device (D2:F0)
- Page 187 and 188: Integrated Graphics Device (D2:F0)
- Page 189 and 190: Integrated Graphics Device (D2:F0)
- Page 191 and 192: Integrated Graphics Device (D2:F1)
- Page 193 and 194: 8.1.3 PCICMD2—PCI Command (D2:F1)
- Page 195 and 196: 8.1.5 RID2—Revision Identificatio
- Page 197 and 198: Integrated Graphics Device (D2:F1)
- Page 199 and 200: Integrated Graphics Device (D2:F1)
- Page 201 and 202: Integrated Graphics Device (D2:F1)
- Page 203 and 204: 8.2 Device 2 - PCI I/O Registers In
- Page 205 and 206: 9 System Address Map System Address
- Page 207 and 208: Figure 9-1. System Address Ranges 4
- Page 209 and 210: Compatible SMRAM Address Range (A_0
- Page 211 and 212: 9.2 Main Memory Address Range (1 MB
- Page 213 and 214: 9.3 PCI Memory Address Range (TOLUD
- Page 215 and 216: 9.3.6 PCI Express* Graphics Attach
- Page 217 and 218: 9.4.1 SMM Space Definition System A
- Page 219 and 220: 9.4.5 SMM Space Decode and Transact
- Page 221 and 222: 9.4.12 Legacy VGA and I/O Range Dec
- Page 223 and 224: 10 Functional Description This chap
- Page 225 and 226: Interleaved Mode Functional Descrip
- Page 227 and 228: 667 MHz (PC 5300) (82945G/82945GC/8
- Page 229 and 230: 10.2.2.2 System Memory Supported Co
- Page 231 and 232: Functional Description Table 10-5.
- Page 233 and 234: 10.3 PCI Express* (Intel ® 82945G/
Integrated Graphics Device (D2:F0) (<strong>Intel®</strong> 82<strong>945G</strong>/82<strong>945G</strong>C/ 82<strong>945G</strong>Z GMCH Only)<br />
7.1.17 CAPPOINT—Capabilities Pointer (D2:F0)<br />
PCI Device: 2<br />
Address Offset: 34h<br />
Default Value: 90h<br />
Access: RO<br />
Size: 8 bits<br />
Bit Access &<br />
Default<br />
7:0 RO<br />
90h<br />
7.1.18 INTRLINE—Interrupt Line (D2:F0)<br />
PCI Device: 2<br />
Address Offset: 3Ch<br />
Default Value: 01h<br />
Access: R/W<br />
Size: 8 bits<br />
Bit Access &<br />
Default<br />
7:0 R/W<br />
01h<br />
7.1.19 INTRPIN—Interrupt Pin (D2:F0)<br />
PCI Device: 2<br />
Address Offset: 3Dh<br />
Default Value: 01h<br />
Access: RO<br />
Size: 8 bits<br />
Bit Access &<br />
Default<br />
7:0 RO<br />
01h<br />
Description<br />
Capabilities Pointer Value: This field contains an offset into the function’s PCI<br />
configuration space for the first item in the New Capabilities Linked List, the MSI<br />
Capabilities ID registers at address 90h, or the Power Management Capabilities<br />
ID registers at address D0h.<br />
Description<br />
Interrupt Connection: This field is used to communicate interrupt line routing<br />
information. POST software writes the routing information into this register as it<br />
initializes and configures the system. The value in this register indicates which<br />
input of the system interrupt controller that is connected to the device’s interrupt<br />
pin.<br />
Description<br />
Interrupt Pin: As a device that only has interrupts associated with a single<br />
function, the IGD specifies INTA# as its interrupt pin.<br />
01h = INTA#.<br />
184 Intel ® 82<strong>945G</strong>/82<strong>945G</strong>Z/82<strong>945G</strong>C GMCH and 82<strong>945P</strong>/82<strong>945P</strong>L MCH Datasheet
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