Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

7.1.11 IOBAR—I/O Base Address (D2:F0)
PCI Device: 2
Address Offset: 14h
Default Value: 00000001h
Access: RO, R/W
Size: 32 bits
Integrated Graphics Device (D2:F0) (Intel® 82945G/82945GC/ 82945GZ GMCH Only)
This register provides the base offset of the I/O registers within Device 2. Bits 15:3 are
programmable allowing the I/O base to be located anywhere in 16-bit I/O address space. Bits 2:1
are fixed and return zero; bit 0 is hardwired to a one indicating that 8 bytes of I/O space are
decoded.
Access to the 8 Bytes of I/O space is allowed in PM state D0 when the I/O Enable bit
(PCICMD[0]) is set to 1. Access is disallowed in PM states D1–D3 or if the I/O Enable is clear or
if Device 2 is turned off. Note that access to this I/O BAR is independent of VGA functionality
within Device 2. Also, note that this mechanism is available only through function 0 of Device 2
and is not duplicated in Function 1.
If accesses to this I/O bar are allowed, the GMCH claims all 8, 16, or 32 bit I/O cycles from the
processor that fall within the 8 Bytes claimed.
Bit Access &
Default
31:16 Reserved
15:3 R/W
0000h
2:1 RO
00b
0 RO
1b
Description
IO Base Address: Set by the operating system, these bits correspond to
address signals 15:3.
Memory Type: Hardwired to 0s to indicate 32-bit address.
Memory / IO Space: Hardwired to 1 to indicate I/O space.
Intel ® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet 181