Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

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Integrated Graphics Device (D2:F0) (Intel® 82945G/82945GC/ 82945GZ GMCH Only) 7.1.3 PCICMD2—PCI Command (D2:F0) PCI Device: 2 Address Offset: 04h Default Value: 0000h Access: RO, R/W Size: 16 bits This 16-bit register provides basic control over the IGD’s ability to respond to PCI cycles. The PCICMD register in the IGD disables the IGD PCI compliant master accesses to main memory. Bit Access & Default 15:11 Reserved 10 R/W 0b 9 RO 0b 8 RO 0b 7 RO 0b 6 RO 0b 5 RO 0b 4 RO 0b 3 RO 0b 2 R/W 0b 1 R/W 0b 0 R/W 0b Description Interrupt Disable: This bit disables the device from asserting INTx#. 0 = Enable the assertion of this device’s INTx# signal. 1 = Disable the assertion of this device’s INTx# signal. DO_INTx messages will not be sent to the DMI. Fast Back-to-Back (FB2B): Hardwired to 0. Not Implemented. SERR Enable (SERRE): Hardwired to 0. Not Implemented. Address/Data Stepping Enable (ADSTEP): Hardwired to 0. Not Implemented. Parity Error Enable (PERRE): Hardwired to 0. Not Implemented. Since the IGD belongs to the category of devices that does not corrupt programs or data in system memory or hard drives, the IGD ignores any parity error that it detects and continues with normal operation. Video Palette Snooping (VPS): This bit is hardwired to 0 to disable snooping. Memory Write and Invalidate Enable (MWIE): Hardwired to 0. The IGD does not support memory write and invalidate commands. Special Cycle Enable (SCE): Hardwired to 0. The IGD ignores special cycles. Bus Master Enable (BME): 0 = Disable IGD bus mastering. 1 = Enable the IGD to function as a PCI compliant master. Memory Access Enable (MAE): This bit controls the IGD’s response to memory space accesses. 0 = Disable. 1 = Enable. I/O Access Enable (IOAE): This bit controls the IGD’s response to I/O space accesses. 0 = Disable. 1 = Enable. 176 Intel ® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
7.1.4 PCISTS2—PCI Status (D2:F0) PCI Device: 2 Address Offset: 06h Default Value: 0090h Access: RO Size: 16 bits Integrated Graphics Device (D2:F0) (Intel® 82945G/82945GC/ 82945GZ GMCH Only) PCISTS2 reports the occurrence of a PCI compliant master abort and PCI compliant target abort. PCISTS also indicates the DEVSEL# timing that has been set by the IGD. Bit Access & Default 15 RO 0b 14 RO 0b 13 RO 0b 12 RO 0b 11 RO 0b 10:9 RO 00b 8 RO 0b 7 RO 1b 6 RO 0b 5 RO 0b 4 RO 1b 3 RO 0b 2:0 Reserved Description Detected Parity Error (DPE): Hardwired to 0. The IGD does not detect parity. Signaled System Error (SSE): Hardwired to 0. The IGD never asserts SERR#. Received Master Abort Status (RMAS): Hardwired to 0. The IGD never gets a Master Abort. Received Target Abort Status (RTAS): Hardwired to 0. The IGD never gets a Target Abort. Signaled Target Abort Status (STAS): Hardwired to 0. The IGD does not use target abort semantics. DEVSEL Timing (DEVT): N/A. Hardwired to 00b. Master Data Parity Error Detected (DPD): Hardwired to 0. Parity Error Response is hardwired to disabled (and the IGD does not do any parity detection). Fast Back-to-Back (FB2B): Hardwired to 1. The IGD accepts fast back-to-back when the transactions are not to the same agent. User Defined Format (UDF): Hardwired to 0. 66 MHz PCI Capable (66C): N/A. Hardwired to 0. Capability List (CLIST): This bit is set to 1 to indicate that the register at 34h provides an offset into the function’s PCI configuration space containing a pointer to the location of the first item in the list. Interrupt Status: This bit reflects the state of the interrupt in the device. Only when the Interrupt Disable bit in the Command register is a 0 and this Interrupt Status bit is a 1, will the devices INTx# signal be asserted. Setting the Interrupt Disable bit to a 1 has no effect on the state of this bit. Intel ® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet 177
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Intel ® 945G/945GZ/945GC/ 945P/945
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Contents 1 Introduction ...........
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4.2.11 C0DRC1—Channel A DRAM Cont
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6.1.16 DMICESTS—DMI Correctable E
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9.4.5 SMM Space Decode and Transact
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11.3 DC Characteristics ...........
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Revision History Rev Description Da
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Intel ® 82945G/82945GZ/82945GC/829
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1 Introduction Introduction The Int
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Figure 1-2. Intel ® 945GZ/82945GC
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1.1 Terminology Term Description Ac
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Term Description TOLM Top Of Low Me
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Introduction � Supports four bank
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Introduction 1.4 Graphics (Intel ®
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1.5 Analog and SDVO Displays (Intel
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2 Signal Description Signal Descrip
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2.1 Host Interface Signals Signal D
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Signal Name Type Description HREQ[4
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2.3 DDR2 DRAM Channel B Interface S
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Signal Description 2.6 Analog Displ
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2.8 Direct Media Interface (DMI) Si
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2.10 Power and Ground Name Voltage
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Interface Signal Name I/O System Me
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Interface Signal Name I/O State Dur
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3 Register Description Register Des
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Register Description Note: A physic
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3.3 Configuration Mechanisms Regist
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3.4 Routing Configuration Accesses
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3.4.2.2 DMI Configuration Accesses
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Bit Access & Default 10:8 R/W 000b
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Host Bridge/DRAM Controller Registe
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4.1 Device 0 Configuration Register
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4.1.4 PCISTS—PCI Status (D0:F0) P
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4.1.7 MLT—Master Latency Timer (D
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4.1.12 EPBAR—Egress Port Base Add
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4.1.19 PAM1—Programmable Attribut
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4.1.25 LAC—Legacy Access Control
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4.1.29 ERRSTS—Error Status (D0:F0
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4.1.31 SKPD—Scratchpad Data (D0:F
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4.2.7 C0DCLKDIS—Channel A DRAM Cl
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4.2.9 C0DRT1—Channel A DRAM Timin
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Bit Access & Default 6:4 R/W 000b 3
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4.2.24 PMSTS—Power Management Sta
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4.3.1 EPESD—EP Element Self Descr
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4.3.3 EPLE1A—EP Link Entry 1 Addr
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Host-PCI Express* Bridge Registers
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Address Offset Host-PCI Express* Br
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5.1.3 PCICMD1—PCI Command (D1:F0)
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5.1.4 PCISTS1—PCI Status (D1:F0)
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5.1.7 CL1—Cache Line Size (D1:F0)
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5.1.12 IOBASE1—I/O Base Address (
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5.1.15 MBASE1—Memory Base Address
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Host-PCI Express* Bridge Registers
Page 125 and 126: 5.1.20 INTRLINE1—Interrupt Line (
Page 127 and 128: Bit Access & Default 2 R/W 0b 1 R/W
Page 129 and 130: Host-PCI Express* Bridge Registers
Page 133 and 134: 5.1.29 MA—Message Address (D1:F0)
Page 135 and 136: 5.1.33 DCAP—Device Capabilities (
Page 137 and 138: 5.1.35 DSTS—Device Status (D1:F0)
Page 139 and 140: 5.1.37 LCTL—Link Control (D1:F0)
Page 141 and 142: 5.1.39 SLOTCAP—Slot Capabilities
Page 143 and 144: 5.1.41 SLOTSTS—Slot Status (D1:F0
Page 145 and 146: 5.1.43 RSTS—Root Status (D1:F0) P
Page 153 and 154: 5.1.56 ESD—Element Self Descripti
Page 157 and 158: 5.1.61 CESTS—Correctable Error St
Page 161 and 162: Direct Media Interface (DMI) RCRB 6
Page 163 and 164: 6.1.3 DMIPVCCAP2—DMI Port VC Capa
Page 165 and 166: 6.1.6 DMIVC0RCTL—DMI VC0 Resource
Page 167 and 168: 6.1.9 DMIVC1RCTL—DMI VC1 Resource
Page 169 and 170: 6.1.13 DMILSTS—DMI Link Status MM
Page 171 and 172: 6.1.15 DMIUEMSK—DMI Uncorrectable
Page 173 and 174: Integrated Graphics Device (D2:F0)
Page 175: Integrated Graphics Device (D2:F0)
Page 179 and 180: 7.1.7 CLS—Cache Line Size (D2:F0)
Page 181 and 182: 7.1.11 IOBAR—I/O Base Address (D2
Page 185 and 186: 7.1.20 MINGNT—Minimum Grant (D2:F
Page 193 and 194: 8.1.3 PCICMD2—PCI Command (D2:F1)
Page 195 and 196: 8.1.5 RID2—Revision Identificatio
Page 203 and 204: 8.2 Device 2 - PCI I/O Registers In
Page 205 and 206: 9 System Address Map System Address
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Page 209 and 210: Compatible SMRAM Address Range (A_0
Page 211 and 212: 9.2 Main Memory Address Range (1 MB
Page 213 and 214: 9.3 PCI Memory Address Range (TOLUD
Page 215 and 216: 9.3.6 PCI Express* Graphics Attach
Page 217 and 218: 9.4.1 SMM Space Definition System A
Page 219 and 220: 9.4.5 SMM Space Decode and Transact
Page 221 and 222: 9.4.12 Legacy VGA and I/O Range Dec
Page 223 and 224: 10 Functional Description This chap
Page 225 and 226: Interleaved Mode Functional Descrip
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667 MHz (PC 5300) (82945G/82945GC/8
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10.2.2.2 System Memory Supported Co
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Functional Description Table 10-5.
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10.3 PCI Express* (Intel ® 82945G/
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Figure 10-2. SDVO Conceptual Block
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Figure 10-3. Concurrent SDVO / PCI
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10.5 Integrated Graphics Device (In
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10.5.3 4X Faster Setup Engine Funct
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10.5.4 Texture Engine Functional De
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10.5.4.8 Pixel Shader Functional De
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Functional Description to determine
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10.5.6 2D Engine Functional Descrip
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10.5.8.1 Cursor Plane Functional De
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Functional Description device is in
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10.6.2 Digital Display Interface Fu
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10.6.2.1.5 Control Bus Functional D
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Figure 10-7 illustrates the various
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11 Electrical Characteristics Elect
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11.1.1 Power Characteristics Table
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Signal Group Electrical Characteris
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11.3 DC Characteristics Table 11-5.
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Symbol Signal Group Electrical Char
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Ballout and Package Information 12
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Ballout and Package Information Fig
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12.2 Ballout Table Ballout and Pack
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Ballout and Package Information EXP
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Ballout and Package Information HA2
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Ballout and Package Information HD6
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Ballout and Package Information RSV
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Ballout and Package Information SDM
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Ballout and Package Information SDQ
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Ballout and Package Information SDQ
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Ballout and Package Information VCC
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Ballout and Package Information VSS
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12.3 Package § Ballout and Package
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Ballout and Package Information Int
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13.2 XOR Test Mode Initialization T
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13.4 XOR Chains Testability Table 1
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Table 13-5. XOR Chain 2 Pin Count B
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Table 13-8. XOR Chain 5 Pin Count B
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Table 13-11. XOR Chain 8 Pin Count
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Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

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