Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...
Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ... Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...
Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only) 5.1.62 CEMSK—Correctable Error Mask (D1:F0) Bus/Dev/Func/Type: 0/1/0/MMR Address Offset: 1D4–1D7h Default Value: 00000000h Access: RO, R/W/S Size: 32 bits This register controls reporting of individual correctable errors by the device (or logic associated with this port) to the PCI Express Root Complex. As these errors are not originating on the other side of a PCI Express link, no PCI Express error message is sent; however, the unmasked error is reported directly to the root control logic. A masked error (respective bit set to 1 in the mask register) has no action taken. There is a mask bit per error bit of the Correctable Error Status register. Bit Access & Default 31:13 Reserved 12 R/W/S 0b Replay Timer Timeout Mask: 0 = Not masked 1 = Masked 11:9 Reserved 8 R/W/S 0b 7 R/W/S 0b 6 R/W/S 0b Replay Number Rollover Mask: 0 = Not masked 1 = Masked Bad DLLP Mask: 0 = Not masked 1 = Masked Bad TLP Mask: 0 = Not masked 1 = Masked 5:1 Reserved 0 R/W/S 0b Receiver Error Mask: 0 = Not masked 1 = Masked Description 158 Intel ® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only) 5.1.63 PEG_SSTS—PCI Express* Sequence Status (D1:F0) PCI Device: 1 Address Offset: 218–21Fh Default Value: 0000000000000FFFh Access: RO Size: 64 bits This register provides PCI Express status reporting that is required by the PCI Express specification. Bit Access & Default 63:60 Reserved 59:48 RO 000h 47:44 Reserved 43:32 RO 000h 31:28 Reserved 27:16 RO 000h 15:12 Reserved 11:0 RO FFFh Description Next Transmit Sequence Number: This field contains the value of the NXT_TRANS_SEQ counter. This counter represents the transmit Sequence number to be applied to the next TLP to be transmitted onto the Link for the first time. Next Packet Sequence Number: This field contains the packet sequence number to be applied to the next TLP to be transmitted or re-transmitted onto the Link. Next Receive Sequence Number: This field contains the sequence number associated with the TLP that is expected to be received next. Last Acknowledged Sequence Number: This field contains the sequence number associated with the last acknowledged TLP. Intel ® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet 159 §
- Page 107 and 108: 4.3.3 EPLE1A—EP Link Entry 1 Addr
- Page 109 and 110: Host-PCI Express* Bridge Registers
- Page 111 and 112: Address Offset Host-PCI Express* Br
- Page 113 and 114: 5.1.3 PCICMD1—PCI Command (D1:F0)
- Page 115 and 116: 5.1.4 PCISTS1—PCI Status (D1:F0)
- Page 117 and 118: 5.1.7 CL1—Cache Line Size (D1:F0)
- Page 119 and 120: 5.1.12 IOBASE1—I/O Base Address (
- Page 121 and 122: 5.1.15 MBASE1—Memory Base Address
- Page 123 and 124: Host-PCI Express* Bridge Registers
- Page 125 and 126: 5.1.20 INTRLINE1—Interrupt Line (
- Page 127 and 128: Bit Access & Default 2 R/W 0b 1 R/W
- Page 129 and 130: Host-PCI Express* Bridge Registers
- Page 131 and 132: Host-PCI Express* Bridge Registers
- Page 133 and 134: 5.1.29 MA—Message Address (D1:F0)
- Page 135 and 136: 5.1.33 DCAP—Device Capabilities (
- Page 137 and 138: 5.1.35 DSTS—Device Status (D1:F0)
- Page 139 and 140: 5.1.37 LCTL—Link Control (D1:F0)
- Page 141 and 142: 5.1.39 SLOTCAP—Slot Capabilities
- Page 143 and 144: 5.1.41 SLOTSTS—Slot Status (D1:F0
- Page 145 and 146: 5.1.43 RSTS—Root Status (D1:F0) P
- Page 147 and 148: Host-PCI Express* Bridge Registers
- Page 149 and 150: Host-PCI Express* Bridge Registers
- Page 151 and 152: Host-PCI Express* Bridge Registers
- Page 153 and 154: 5.1.56 ESD—Element Self Descripti
- Page 155 and 156: Host-PCI Express* Bridge Registers
- Page 157: 5.1.61 CESTS—Correctable Error St
- Page 161 and 162: Direct Media Interface (DMI) RCRB 6
- Page 163 and 164: 6.1.3 DMIPVCCAP2—DMI Port VC Capa
- Page 165 and 166: 6.1.6 DMIVC0RCTL—DMI VC0 Resource
- Page 167 and 168: 6.1.9 DMIVC1RCTL—DMI VC1 Resource
- Page 169 and 170: 6.1.13 DMILSTS—DMI Link Status MM
- Page 171 and 172: 6.1.15 DMIUEMSK—DMI Uncorrectable
- Page 173 and 174: Integrated Graphics Device (D2:F0)
- Page 175 and 176: Integrated Graphics Device (D2:F0)
- Page 177 and 178: 7.1.4 PCISTS2—PCI Status (D2:F0)
- Page 179 and 180: 7.1.7 CLS—Cache Line Size (D2:F0)
- Page 181 and 182: 7.1.11 IOBAR—I/O Base Address (D2
- Page 183 and 184: Integrated Graphics Device (D2:F0)
- Page 185 and 186: 7.1.20 MINGNT—Minimum Grant (D2:F
- Page 187 and 188: Integrated Graphics Device (D2:F0)
- Page 189 and 190: Integrated Graphics Device (D2:F0)
- Page 191 and 192: Integrated Graphics Device (D2:F1)
- Page 193 and 194: 8.1.3 PCICMD2—PCI Command (D2:F1)
- Page 195 and 196: 8.1.5 RID2—Revision Identificatio
- Page 197 and 198: Integrated Graphics Device (D2:F1)
- Page 199 and 200: Integrated Graphics Device (D2:F1)
- Page 201 and 202: Integrated Graphics Device (D2:F1)
- Page 203 and 204: 8.2 Device 2 - PCI I/O Registers In
- Page 205 and 206: 9 System Address Map System Address
- Page 207 and 208: Figure 9-1. System Address Ranges 4
Host-PCI <strong>Express</strong>* Bridge Registers (D1:F0) (<strong>Intel®</strong> 82<strong>945G</strong>/82<strong>945G</strong>C/82<strong>945P</strong>/82<strong>945P</strong>L Only)<br />
5.1.63 PEG_SSTS—PCI <strong>Express</strong>* Sequence Status (D1:F0)<br />
PCI Device: 1<br />
Address Offset: 218–21Fh<br />
Default Value: 0000000000000FFFh<br />
Access: RO<br />
Size: 64 bits<br />
This register provides PCI <strong>Express</strong> status reporting that is required by the PCI <strong>Express</strong><br />
specification.<br />
Bit Access &<br />
Default<br />
63:60 Reserved<br />
59:48 RO<br />
000h<br />
47:44 Reserved<br />
43:32 RO<br />
000h<br />
31:28 Reserved<br />
27:16 RO<br />
000h<br />
15:12 Reserved<br />
11:0 RO<br />
FFFh<br />
Description<br />
Next Transmit Sequence Number: This field contains the value of the<br />
NXT_TRANS_SEQ counter. This counter represents the transmit Sequence<br />
number to be applied to the next TLP to be transmitted onto the Link for the first<br />
time.<br />
Next Packet Sequence Number: This field contains the packet sequence<br />
number to be applied to the next TLP to be transmitted or re-transmitted onto the<br />
Link.<br />
Next Receive Sequence Number: This field contains the sequence number<br />
associated with the TLP that is expected to be received next.<br />
Last Acknowledged Sequence Number: This field contains the sequence<br />
number associated with the last acknowledged TLP.<br />
Intel ® 82<strong>945G</strong>/82<strong>945G</strong>/82<strong>945G</strong>C GMCH and 82<strong>945P</strong>/82<strong>945P</strong>L MCH Datasheet 159<br />
§
Change language