Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...
Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ... Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...
Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only) 5.1.62 CEMSK—Correctable Error Mask (D1:F0) Bus/Dev/Func/Type: 0/1/0/MMR Address Offset: 1D4–1D7h Default Value: 00000000h Access: RO, R/W/S Size: 32 bits This register controls reporting of individual correctable errors by the device (or logic associated with this port) to the PCI Express Root Complex. As these errors are not originating on the other side of a PCI Express link, no PCI Express error message is sent; however, the unmasked error is reported directly to the root control logic. A masked error (respective bit set to 1 in the mask register) has no action taken. There is a mask bit per error bit of the Correctable Error Status register. Bit Access & Default 31:13 Reserved 12 R/W/S 0b Replay Timer Timeout Mask: 0 = Not masked 1 = Masked 11:9 Reserved 8 R/W/S 0b 7 R/W/S 0b 6 R/W/S 0b Replay Number Rollover Mask: 0 = Not masked 1 = Masked Bad DLLP Mask: 0 = Not masked 1 = Masked Bad TLP Mask: 0 = Not masked 1 = Masked 5:1 Reserved 0 R/W/S 0b Receiver Error Mask: 0 = Not masked 1 = Masked Description 158 Intel ® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only) 5.1.63 PEG_SSTS—PCI Express* Sequence Status (D1:F0) PCI Device: 1 Address Offset: 218–21Fh Default Value: 0000000000000FFFh Access: RO Size: 64 bits This register provides PCI Express status reporting that is required by the PCI Express specification. Bit Access & Default 63:60 Reserved 59:48 RO 000h 47:44 Reserved 43:32 RO 000h 31:28 Reserved 27:16 RO 000h 15:12 Reserved 11:0 RO FFFh Description Next Transmit Sequence Number: This field contains the value of the NXT_TRANS_SEQ counter. This counter represents the transmit Sequence number to be applied to the next TLP to be transmitted onto the Link for the first time. Next Packet Sequence Number: This field contains the packet sequence number to be applied to the next TLP to be transmitted or re-transmitted onto the Link. Next Receive Sequence Number: This field contains the sequence number associated with the TLP that is expected to be received next. Last Acknowledged Sequence Number: This field contains the sequence number associated with the last acknowledged TLP. Intel ® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet 159 §
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Host-PCI <strong>Express</strong>* Bridge Registers (D1:F0) (<strong>Intel®</strong> 82<strong>945G</strong>/82<strong>945G</strong>C/82<strong>945P</strong>/82<strong>945P</strong>L Only)<br />
5.1.62 CEMSK—Correctable Error Mask (D1:F0)<br />
Bus/Dev/Func/Type: 0/1/0/MMR<br />
Address Offset: 1D4–1D7h<br />
Default Value: 00000000h<br />
Access: RO, R/W/S<br />
Size: 32 bits<br />
This register controls reporting of individual correctable errors by the device (or logic associated<br />
with this port) to the PCI <strong>Express</strong> Root Complex. As these errors are not originating on the other<br />
side of a PCI <strong>Express</strong> link, no PCI <strong>Express</strong> error message is sent; however, the unmasked error is<br />
reported directly to the root control logic. A masked error (respective bit set to 1 in the mask<br />
register) has no action taken. There is a mask bit per error bit of the Correctable Error Status<br />
register.<br />
Bit Access &<br />
Default<br />
31:13 Reserved<br />
12 R/W/S<br />
0b<br />
Replay Timer Timeout Mask:<br />
0 = Not masked<br />
1 = Masked<br />
11:9 Reserved<br />
8 R/W/S<br />
0b<br />
7 R/W/S<br />
0b<br />
6 R/W/S<br />
0b<br />
Replay Number Rollover Mask:<br />
0 = Not masked<br />
1 = Masked<br />
Bad DLLP Mask:<br />
0 = Not masked<br />
1 = Masked<br />
Bad TLP Mask:<br />
0 = Not masked<br />
1 = Masked<br />
5:1 Reserved<br />
0 R/W/S<br />
0b<br />
Receiver Error Mask:<br />
0 = Not masked<br />
1 = Masked<br />
Description<br />
158 Intel ® 82<strong>945G</strong>/82<strong>945G</strong>Z/82<strong>945G</strong>C GMCH and 82<strong>945P</strong>/82<strong>945P</strong>L MCH Datasheet