Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

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Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only) 5.1.57 LE1D—Link Entry 1 Description (D1:F0) PCI Device: 1 Address Offset: 150–153h Default Value: 00000000h Access: RO, R/WO Size: 32 bits This register contains the first part of a Link Entry, which declares an internal link to another Root Complex Element. Bit Access & Default 31:24 RO 00h 23:16 R/WO 00h 15:2 Reserved 1 RO 0b 0 R/WO 0b Description Target Port Number: This field specifies the port number associated with the element targeted by this link entry (Egress Port). The target port number is with respect to the component that contains this element as specified by the target component ID. Target Component ID: This field identifies the physical or logical component that is targeted by this link entry. Link Type: This bit identifies that the link points to memory-mapped space (for RCRB). The link address specifies the 64-bit base address of the target RCRB. Link Valid: 0 = Link Entry is not valid and will be ignored. 1 = Link Entry specifies a valid link. 5.1.58 LE1A—Link Entry 1 Address (D1:F0) PCI Device: 1 Address Offset: 158158–15Fh Default Value: 0000000000000000h Access: R/WO Size: 64 bits This register contains the second part of a Link Entry that declares an internal link to another Root Complex element. Bit Access & Default 63:32 Reserved 31:12 R/WO 0 0000h 11:0 Reserved Description Link Address: This field contains the memory-mapped base address of the RCRB that is the target element (Egress Port) for this link entry. 154 Intel ® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only) 5.1.59 UESTS—Uncorrectable Error Status (D1:F0) Bus/Dev/Func/Type: 0/1/0/MMR Address Offset: 1C4–1C7h Default Value: 00000000h Access: RO, R/WC/S Size: 32 bits This register reports error status of individual error sources on a PCI Express device. An individual error status bit that is set indicates that a particular error occurred. Note: Software clears an error status by writing a 1 to the respective bit. Bit Access & Default 31:2 1 20 R/WC/S 0b Reserved 19 Reserved 18 R/WC/S 0b 17 R/WC/S 0b 16 R/WC/S 0b 15 Reserved 14 R/WC/S 0b 13:5 Reserved 4 R/WC/S 0b 3:0 Reserved Unsupported Request Error Status: 0 = Error did Not occur 1 = Error occurred Malformed TLP Status: 0 = Error did Not occur 1 = Error occurred Receiver Overflow Status: 0 = Error did Not occur 1 = Error occurred Unexpected Completion Status: 0 = Error did Not occur 1 = Error occurred Completion Timeout Status: 0 = Error did Not occur 1 = Error occurred Description Data Link Protocol Error Status (DLPES): The Data Link Layer Protocol Error that causes this bit to be set will also cause the Fatal Error Detected bit (bit 2) in the DSTS (Device Status, D1:F0) to be set if not already set. 0 = Error did Not occur 1 = Error occurred Intel ® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet 155
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Intel ® 945G/945GZ/945GC/ 945P/945
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Contents 1 Introduction ...........
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4.2.11 C0DRC1—Channel A DRAM Cont
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6.1.16 DMICESTS—DMI Correctable E
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9.4.5 SMM Space Decode and Transact
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11.3 DC Characteristics ...........
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Revision History Rev Description Da
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Intel ® 82945G/82945GZ/82945GC/829
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1 Introduction Introduction The Int
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Figure 1-2. Intel ® 945GZ/82945GC
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1.1 Terminology Term Description Ac
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Term Description TOLM Top Of Low Me
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Introduction � Supports four bank
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Introduction 1.4 Graphics (Intel ®
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1.5 Analog and SDVO Displays (Intel
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2 Signal Description Signal Descrip
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2.1 Host Interface Signals Signal D
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Signal Name Type Description HREQ[4
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2.3 DDR2 DRAM Channel B Interface S
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Signal Description 2.6 Analog Displ
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2.8 Direct Media Interface (DMI) Si
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2.10 Power and Ground Name Voltage
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Interface Signal Name I/O System Me
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Interface Signal Name I/O State Dur
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3 Register Description Register Des
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Register Description Note: A physic
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3.3 Configuration Mechanisms Regist
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3.4 Routing Configuration Accesses
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3.4.2.2 DMI Configuration Accesses
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Bit Access & Default 10:8 R/W 000b
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Host Bridge/DRAM Controller Registe
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4.1 Device 0 Configuration Register
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4.1.4 PCISTS—PCI Status (D0:F0) P
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4.1.7 MLT—Master Latency Timer (D
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4.1.12 EPBAR—Egress Port Base Add
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4.1.19 PAM1—Programmable Attribut
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4.1.25 LAC—Legacy Access Control
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4.1.29 ERRSTS—Error Status (D0:F0
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4.1.31 SKPD—Scratchpad Data (D0:F
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4.2.7 C0DCLKDIS—Channel A DRAM Cl
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4.2.9 C0DRT1—Channel A DRAM Timin
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Bit Access & Default 6:4 R/W 000b 3
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Page 103 and 104: 4.2.24 PMSTS—Power Management Sta
Page 105 and 106: 4.3.1 EPESD—EP Element Self Descr
Page 107 and 108: 4.3.3 EPLE1A—EP Link Entry 1 Addr
Page 109 and 110: Host-PCI Express* Bridge Registers
Page 111 and 112: Address Offset Host-PCI Express* Br
Page 113 and 114: 5.1.3 PCICMD1—PCI Command (D1:F0)
Page 115 and 116: 5.1.4 PCISTS1—PCI Status (D1:F0)
Page 117 and 118: 5.1.7 CL1—Cache Line Size (D1:F0)
Page 119 and 120: 5.1.12 IOBASE1—I/O Base Address (
Page 121 and 122: 5.1.15 MBASE1—Memory Base Address
Page 125 and 126: 5.1.20 INTRLINE1—Interrupt Line (
Page 127 and 128: Bit Access & Default 2 R/W 0b 1 R/W
Page 133 and 134: 5.1.29 MA—Message Address (D1:F0)
Page 135 and 136: 5.1.33 DCAP—Device Capabilities (
Page 137 and 138: 5.1.35 DSTS—Device Status (D1:F0)
Page 139 and 140: 5.1.37 LCTL—Link Control (D1:F0)
Page 141 and 142: 5.1.39 SLOTCAP—Slot Capabilities
Page 143 and 144: 5.1.41 SLOTSTS—Slot Status (D1:F0
Page 145 and 146: 5.1.43 RSTS—Root Status (D1:F0) P
Page 153: 5.1.56 ESD—Element Self Descripti
Page 157 and 158: 5.1.61 CESTS—Correctable Error St
Page 161 and 162: Direct Media Interface (DMI) RCRB 6
Page 163 and 164: 6.1.3 DMIPVCCAP2—DMI Port VC Capa
Page 165 and 166: 6.1.6 DMIVC0RCTL—DMI VC0 Resource
Page 167 and 168: 6.1.9 DMIVC1RCTL—DMI VC1 Resource
Page 169 and 170: 6.1.13 DMILSTS—DMI Link Status MM
Page 171 and 172: 6.1.15 DMIUEMSK—DMI Uncorrectable
Page 173 and 174: Integrated Graphics Device (D2:F0)
Page 177 and 178: 7.1.4 PCISTS2—PCI Status (D2:F0)
Page 179 and 180: 7.1.7 CLS—Cache Line Size (D2:F0)
Page 181 and 182: 7.1.11 IOBAR—I/O Base Address (D2
Page 185 and 186: 7.1.20 MINGNT—Minimum Grant (D2:F
Page 193 and 194: 8.1.3 PCICMD2—PCI Command (D2:F1)
Page 195 and 196: 8.1.5 RID2—Revision Identificatio
Page 203 and 204: 8.2 Device 2 - PCI I/O Registers In
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9 System Address Map System Address
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Figure 9-1. System Address Ranges 4
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Compatible SMRAM Address Range (A_0
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9.2 Main Memory Address Range (1 MB
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9.3 PCI Memory Address Range (TOLUD
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9.3.6 PCI Express* Graphics Attach
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9.4.1 SMM Space Definition System A
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9.4.5 SMM Space Decode and Transact
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9.4.12 Legacy VGA and I/O Range Dec
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10 Functional Description This chap
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Interleaved Mode Functional Descrip
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667 MHz (PC 5300) (82945G/82945GC/8
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10.2.2.2 System Memory Supported Co
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Functional Description Table 10-5.
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10.3 PCI Express* (Intel ® 82945G/
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Figure 10-2. SDVO Conceptual Block
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Figure 10-3. Concurrent SDVO / PCI
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10.5 Integrated Graphics Device (In
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10.5.3 4X Faster Setup Engine Funct
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10.5.4 Texture Engine Functional De
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10.5.4.8 Pixel Shader Functional De
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Functional Description to determine
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10.5.6 2D Engine Functional Descrip
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10.5.8.1 Cursor Plane Functional De
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Functional Description device is in
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10.6.2 Digital Display Interface Fu
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10.6.2.1.5 Control Bus Functional D
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Figure 10-7 illustrates the various
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11 Electrical Characteristics Elect
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11.1.1 Power Characteristics Table
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Signal Group Electrical Characteris
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11.3 DC Characteristics Table 11-5.
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Symbol Signal Group Electrical Char
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Ballout and Package Information 12
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Ballout and Package Information Fig
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12.2 Ballout Table Ballout and Pack
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Ballout and Package Information EXP
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Ballout and Package Information HA2
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Ballout and Package Information HD6
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Ballout and Package Information RSV
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Ballout and Package Information SDM
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Ballout and Package Information SDQ
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Ballout and Package Information SDQ
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Ballout and Package Information VCC
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Ballout and Package Information VSS
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12.3 Package § Ballout and Package
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Ballout and Package Information Int
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13.2 XOR Test Mode Initialization T
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13.4 XOR Chains Testability Table 1
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Table 13-5. XOR Chain 2 Pin Count B
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Table 13-8. XOR Chain 5 Pin Count B
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Table 13-11. XOR Chain 8 Pin Count
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Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

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