Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...
Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ... Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...
Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only) 5.1.42 RCTL—Root Control (D1:F0) PCI Device: 1 Address Offset: BCh Default Value: 0000h Access: R/W Size: 16 bits This register allows control of PCI Express Root Complex specific parameters. The system error control bits in this register determine if corresponding SERRs are generated when the device detects an error (reported in this device’s Device Status register) or when an error message is received across the link. Reporting of SERR, as controlled by these bits, takes precedence over the SERR Enable in the PCI Command register. Bit Access & Default 15:4 Reserved 3 R/W 0b 2 R/W 0b 1 R/W 0b 0 R/W 0b PME Interrupt Enable: Description 0 = Disable. No interrupts are generated as a result of receiving PME messages. 1 = Enables interrupt generation upon receipt of a PME message as reflected in the PME Status bit of the Root Status register. A PME interrupt is also generated if the PME Status bit of the Root Status register is set when this bit is set from a cleared state. System Error on Fatal Error Enable: This bit controls the root complex’s response to fatal errors. 0 = Disable. No SERR generated on receipt of fatal error. 1 = SERR is generated if a fatal error is reported by any of the devices in the hierarchy associated with this root port, or by the Root Port itself. System Error on Non-Fatal Uncorrectable Error Enable: This bit controls the Root Complex’s response to non-fatal errors. 0 = Disable. No SERR generated on receipt of non-fatal error. 1 = SERR is generated if a non-fatal error is reported by any of the devices in the hierarchy associated with this Root Port, or by the Root Port itself. System Error on Correctable Error Enable: This bit controls the Root Complex’s response to correctable errors. 0 = Disable. No SERR generated on receipt of correctable error. 1 = SERR is generated if a correctable error is reported by any of the devices in the hierarchy associated with this Root Port, or by the Root Port itself. 144 Intel ® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet
5.1.43 RSTS—Root Status (D1:F0) PCI Device: 1 Address Offset: C0–C3h Default Value: 00000000h Access: RO, R/WC Size: 32 bits Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only) This register provides information about PCI Express Root Complex specific parameters. Bit Access & Default 31:18 Reserved 17 RO 0b 16 R/WC 0b 15:0 RO 0000h PME Pending: 0 = PME Not pending. Description 1 = Another PME is pending when the PME Status bit is set. When the PME Status bit is cleared by software; the PME is delivered by hardware by setting the PME Status bit again and updating the Requestor ID appropriately. The PME pending bit is cleared by hardware if no more PMEs are pending. PME Status: 0 = Requestor ID did Not assert PME. 1 = Requestor ID indicated in the PME Requestor ID field asserted PME. Subsequent PMEs are kept pending until the status register is cleared by writing a 1 to this field. PME Requestor ID: This field indicates the PCI requestor ID of the last PME requestor. Intel ® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet 145
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- Page 133 and 134: 5.1.29 MA—Message Address (D1:F0)
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5.1.43 RSTS—Root Status (D1:F0)<br />
PCI Device: 1<br />
Address Offset: C0–C3h<br />
Default Value: 00000000h<br />
Access: RO, R/WC<br />
Size: 32 bits<br />
Host-PCI <strong>Express</strong>* Bridge Registers (D1:F0) (<strong>Intel®</strong> 82<strong>945G</strong>/82<strong>945G</strong>C/82<strong>945P</strong>/82<strong>945P</strong>L Only)<br />
This register provides information about PCI <strong>Express</strong> Root Complex specific parameters.<br />
Bit Access &<br />
Default<br />
31:18 Reserved<br />
17 RO<br />
0b<br />
16 R/WC<br />
0b<br />
15:0 RO<br />
0000h<br />
PME Pending:<br />
0 = PME Not pending.<br />
Description<br />
1 = Another PME is pending when the PME Status bit is set. When the PME<br />
Status bit is cleared by software; the PME is delivered by hardware by<br />
setting the PME Status bit again and updating the Requestor ID<br />
appropriately. The PME pending bit is cleared by hardware if no more<br />
PMEs are pending.<br />
PME Status:<br />
0 = Requestor ID did Not assert PME.<br />
1 = Requestor ID indicated in the PME Requestor ID field asserted PME.<br />
Subsequent PMEs are kept pending until the status register is cleared by<br />
writing a 1 to this field.<br />
PME Requestor ID: This field indicates the PCI requestor ID of the last PME<br />
requestor.<br />
Intel ® 82<strong>945G</strong>/82<strong>945G</strong>/82<strong>945G</strong>C GMCH and 82<strong>945P</strong>/82<strong>945P</strong>L MCH Datasheet 145
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