Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only)
5.1.42 RCTL—Root Control (D1:F0)
PCI Device: 1
Address Offset: BCh
Default Value: 0000h
Access: R/W
Size: 16 bits
This register allows control of PCI Express Root Complex specific parameters. The system error
control bits in this register determine if corresponding SERRs are generated when the device
detects an error (reported in this device’s Device Status register) or when an error message is
received across the link. Reporting of SERR, as controlled by these bits, takes precedence over
the SERR Enable in the PCI Command register.
Bit Access &
Default
15:4 Reserved
3 R/W
0b
2 R/W
0b
1 R/W
0b
0 R/W
0b
PME Interrupt Enable:
Description
0 = Disable. No interrupts are generated as a result of receiving PME
messages.
1 = Enables interrupt generation upon receipt of a PME message as reflected in
the PME Status bit of the Root Status register. A PME interrupt is also
generated if the PME Status bit of the Root Status register is set when this
bit is set from a cleared state.
System Error on Fatal Error Enable: This bit controls the root complex’s
response to fatal errors.
0 = Disable. No SERR generated on receipt of fatal error.
1 = SERR is generated if a fatal error is reported by any of the devices in the
hierarchy associated with this root port, or by the Root Port itself.
System Error on Non-Fatal Uncorrectable Error Enable: This bit controls the
Root Complex’s response to non-fatal errors.
0 = Disable. No SERR generated on receipt of non-fatal error.
1 = SERR is generated if a non-fatal error is reported by any of the devices in
the hierarchy associated with this Root Port, or by the Root Port itself.
System Error on Correctable Error Enable: This bit controls the Root
Complex’s response to correctable errors.
0 = Disable. No SERR generated on receipt of correctable error.
1 = SERR is generated if a correctable error is reported by any of the devices in
the hierarchy associated with this Root Port, or by the Root Port itself.
144 Intel ® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet