Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

5.1.37 LCTL—Link Control (D1:F0)
PCI Device: 1
Address Offset: B0–B1
Default Value: 0000h
Access: RO, R/W
Size: 16 bits
This register allows control of the PCI Express link.
Bit Access &
Default
15:8 Reserved
7 R/W
0h
6 R/W
0b
5 R/W
0b
4 R/W
0b
3 RO
0b
2 Reserved
1:0 R/W
00b
Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only)
Description
Reserved. Must be 0 when writing this register.
Common Clock Configuration: Components use this common clock
configuration information to report the correct L0s exit latency.
The state of this bit affects the L0s exit latency reported in LCAP [14:12] and the
N_FTS value advertised during link training.
0 = This component and the component at the opposite end of this Link are
operating with asynchronous reference clock.
1 = This component and the component at the opposite end of this Link are
operating with a distributed common reference clock.
Retrain Link: This bit always returns 0 when read. This bit is cleared
automatically (no need to write a 0).
0 = Normal operation
1 = Full Link retraining is initiated by directing the Physical Layer LTSSM from L0
or L0s states to the recovery state.
Link Disable: The link retraining happens automatically on a 0-to-1 transition, just
like when coming out of reset. Writes to this bit are immediately reflected in the
value read from the bit, regardless of actual Link state.
0 = Enable. Normal operation
1 = Link is disabled. This forces the LTSSM to transition to the disabled state (via
Recovery) from L0 or L0s states.
Read Completion Boundary (RCB) : Hardwired to 0 to indicate 64 byte.
Active State PM: This field controls the level of active state power management
supported on the given link.
00 = Disabled
01 = L0s Entry Supported
10 = Reserved
11 = L0s Entry Supported
Intel ® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet 139