Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only)
5.1.34 DCTL—Device Control (D1:F0)
PCI Device: 1
Address Offset: A8–A9h
Default Value: 0000h
Access: R/W
Size: 16 bits
This register provides control for PCI Express device specific capabilities.
Note: The error reporting enable bits are in reference to errors detected by this device, not error
messages received across the link. The reporting of error messages (ERR_CORR,
ERR_NONFATAL, ERR_FATAL) received by Root Port is controlled exclusively by the Root
Port Command register.
Bit Access &
Default
15:8 Reserved
7:5 R/W
000b
4 Reserved
3 R/W
0b
2 R/W
0b
1 R/W
0b
0 R/W
0b
Max Payload Size:
Description
000 = 128B maximum supported payload for Transaction Layer Packets (TLP).
As a receiver, the Device must handle TLPs as large as the set value. As
a transmitter, the Device must not generate TLPs exceeding the set
value.
001–111 = Reserved.
Unsupported Request Reporting Enable:
0 = Disable.
1 = Enable. Unsupported requests will be reported.
NOTE: Reporting of error messages received by Root Port is controlled
exclusively by Root Control register.
Fatal Error Reporting Enable:
0 = Disable.
1 = Enable. Fatal errors will be reported. For a Root Port, the reporting of fatal
errors is internal to the root. No external ERR_FATAL message is
generated.
Non-Fatal Error Reporting Enable:
0 = Disable.
1 = Enable. Non-fatal errors will be reported. For a Root Port, the reporting of
non-fatal errors is internal to the root. No external ERR_NONFATAL
message is generated. Uncorrectable errors can result in degraded
performance.
Correctable Error Reporting Enable:
0 = Disable.
1 = Enable. Correctable errors will be reported. For a Root Port, the reporting of
correctable errors is internal to the root. No external ERR_CORR message
is generated.
136 Intel ® 82945G/82945GZ/82945GC GMCH and 82945P/82945PL MCH Datasheet