Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

5.1.29 MA—Message Address (D1:F0)
PCI Device: 1
Address Offset: 94h
Default Value: 00000000h
Access: RO, R/W
Size: 32 bits
Bit Access &
Default
31:2 R/W
00000000h
1:0 RO
00b
5.1.30 MD—Message Data (D1:F0)
PCI Device: 1
Address Offset: 98–99h
Default Value: 0000h
Access: R/W
Size: 16 bits
Bit Access &
Default
15:0 R/W
0000h
Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only)
Description
Message Address: This field is used by system software to assign a MSI
address to the device. The device handles a MSI by writing the padded
contents of the MD register to this address.
Force DWord Align: Hardwired to 0s so that addresses assigned by system
software are always aligned on a DWord address boundary.
Description
Message Data: This field is the base message data pattern assigned by system
software and used to handle a MSI from the device.
When the device must generate an interrupt request, it writes a 32-bit value to
the memory address specified in the MA register. The upper 16 bits are always
set to 0. This register supplies the lower 16 bits.
Intel ® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet 133