Intel® 945G/945GZ/945GC/ 945P/945PL Express Chipset Family ...

Bit Access &
Default
2 R/W
0b
1 R/W
0b
0 RO
0b
Host-PCI Express* Bridge Registers (D1:F0) (Intel® 82945G/82945GC/82945P/82945PL Only)
Description
ISA Enable (ISAEN): This bit is used to exclude legacy resource decode to route
ISA resources to the legacy decode path. This bit modifies the response by the
(G)MCH to an I/O access issued by the processor that target ISA I/O addresses.
This applies only to I/O addresses that are enabled by the IOBASE and IOLIMIT
registers.
0 = All addresses defined by the IOBASE and IOLIMIT for processor I/O
transactions will be mapped to PCI Express.
1 = (G)MCH will not forward to PCI Express any I/O transactions addressing the
last 768 bytes in each 1-KB block, even if the addresses are within the range
defined by the IOBASE and IOLIMIT registers. Instead of going to PCI
Express, these cycles are forwarded to DMI where they can be subtractively
or positively claimed by the ISA bridge.
SERR Enable (SERREN):
0 = Disable. No forwarding of error messages from secondary side to primary
side that could result in a SERR.
1 = Enable. ERR_COR, ERR_NONFATAL, and ERR_FATAL messages result in
SERR message when individually enabled by the Root Control register.
Parity Error Response Enable (PEREN): This bit controls whether or not the
Master Data Parity Error bit in the Secondary Status register is set when the
(G)MCH receives across the link (upstream) a Read Data Completion Poisoned
TLP.
0 = Disable. Master Data Parity Error bit in Secondary Status register cannot be
set.
1 = Enable. Master Data Parity Error bit in Secondary Status register can be set.
Intel ® 82945G/82945G/82945GC GMCH and 82945P/82945PL MCH Datasheet 127